| This work is focused on the development of a Java co-processor architecture, called Frappé or Φ, that is suitable for operating networked appliances and is efficient for hardware implementation. Specifically, the goal of this research was to define the most effective single-chip architecture for a network appliance, which can be efficiently implemented so that (a) it can execute native Java programs, (b) it has low power consumption, (c) it is cost-effective and (d) it has a seamless network interface.; Φ incorporates a six-stage pipeline, a decode unit that can decode and fold up to three instruction per cycle, a generic interface to a host processor, a Stack Frame Buffer for expediting access to method frames and a Constant Pool Cache for accelerating the use of class constant pools. About 66% of the dynamic instruction count of Java programs is executed by Φ in hardware in one cycle, 30% is implemented in microcode and 4% is trapped and emulated in software.; The SPECjvm98 benchmark suite and a demo graphical application were used to make several design tradeoffs. Analysis of experimental data has led to the design of a multi-port Stack Frame Buffer, which essentially transforms the Java execution stack to a register file with automatic overflow/underflow management, and to the design of the novel Constant Pool Cache, which is an alternative to the “quick” opcodes used by Sun Microsystems' JVMs without compromising performance.; Several software and hardware solutions for accelerating the execution of Java programs are discussed and compared to Φ in this dissertation in order to assess the impact of Φ's novel architecture features on its performance. Frappé is superior to all software solutions and, as the results from the EmbeddedCaffeineMark 3.0 benchmark show, performs better than other embedded Java accelerators. The score attained by Frappé is 9.4 EmbeddedCaffeineMarks/MHz, which is higher than the score of other Java accelerators. |
