Design, implementation and use of the MIRV experimental compiler for computer architecture research

This dissertation introduces MIRV, an experimental compiler developed for computer architecture research. We discuss the design and implementation of the compiler and use it to conduct studies of various techniques to tolerate memory latency. On the instruction side, a thorough examination of hardware and software prefetching techniques is performed to evaluate their utility on several modern computer designs. Various points of ambiguity in the literature are identified and the consequences of their specification are studied. A framework for describing software instruction prefetching algorithms is developed and extensions to current techniques are analyzed. Previous research has shown that larger data register sets than are currently available in modern microprocessors are desirable. Various extensions to this research are explored to further increase the utility of the register file.