III-V to silicon wafer fusion for the fused silicon/indium gallium arsenide avalanche photodiode

Wafer fusion is a novel technique for integrating otherwise incompatible materials in order to reap the benefits of both materials in one device. Work was done at the University of California at San Diego (UCSD) to investigate wafer fusion between III–V compound semiconductor and silicon (Si). This was done to support the burgeoning research on the wafer fused Silicon-Indium Gallium Arsenide Avalanche Photodiode (Si/InGaAs APD), which requires the use of both materials in an extremely critical manner. The main goals of this author's work were primarily to enable the device research and then to form a deeper understanding of the processes involved in the fusion technique used to fabricate the required material.; The first goal was achieved successfully through the creation of a Low Thermal Stress (LTS) process of wafer fusion. This technique required the development of a great number of process-related advances. The final result of this work was the design and implementation of a high yield scalable process for fabrication of fused InGaAs layer on Si substrates for use in devices.; The second goal was pursued with a particular focus on the issues of thermal stress. In doing so detailed models for the materials' behaviors were developed and used to describe the observed phenomena. Using Nomarski-mode optical microscopy and high resolution X-ray diffraction techniques it was shown that the LTS samples had fewer defects than their high thermal stress-processed counter parts. The value of these differences was illuminated clearly by device fabrication showing dramatically improved performance when using the LTS method.