| A fully integrated low-power and low-voltage quad-band (GSM 850, E-GSM 900, DCS 1800 and PCS 1900) GSM CMOS transmitter is proposed in this work. It exploits the concept of closed loop PLL upconversion using a modulated fractional-N frequency synthesizer. Through clever circuit techniques, this architecture uses type-I loop and achieve a mostly digital fully integrated IC with no external components. The cutoff frequency of the first pole is well controlled through switch capacitor techniques. This makes the closed loop transfer function of the PLL well defined with just two unknown namely the gain of the phase detector, Kp and the VCO gain, Kv. Any deviation of the phase detector gain from the desired value is first calibrated out using an automatic Kp tuning block. The overall mismatch between the compensated filter and the closed loop PLL transfer function is calibrated through a fully digital auto-calibration circuit.; The present architecture utilizes a single VCO with digital coarse tuning circuit to cover for the quad-band frequencies in addition to any frequency shift due to process variations. A divide-by-two circuit has been inserted to separate the high-band and low-band outputs. A switch has been included into each pre-amplifier design so that either band can be selected through multiplexing the switches. A third-order multi-stage noise shaping (MASH) sigma-delta modulator with 26 bits of input achieves 0.39 Hz of frequency resolution using a reference frequency of 26 MHz. The present quad-band GSM transmitter has been implemented in a 0.13mum CMOS technology. It meets all the quad-band GSM transmitter specifications with current consumption of only 28mA from a 1.5V power supply. |
