| Advances in silicon CMOS technologies provide increases in device speed and wiring density, accompanied by reduced power supply voltages. These advances also result in rapid voltage swings, increased current density and reduced noise margins. This leads to data integrity problems, primarily due to simultaneous switching noise generated by core logic switching, I/O circuitry or both. The need to control induced noise has become a major design effort for both chip and package designers as we move into the realm of giga-scale integration and giga-hertz frequencies. This research explores architecture level methodologies to attenuate the problem in the early phases of a design cycle, thereby providing solutions that can complement the current circuit level techniques. An architectural model of power supply noise has been developed that combines power supply wiring organization with workload driven models of on-chip activity to more accurately predict induced noise. Hardware and software techniques to reduce switching noise have also been perused.;This research aims to develop an architectural assessment of chip ground bounce (also known as the ∂I/∂t problem). This architectural approach complements circuit level techniques that are currently in use in integrated circuits. The developed architectural and software techniques have been demonstrated to reduce the extent of noise in the power supply by reducing the source of rapid current switching. An attempt has been made to characterize the high-level parameters that create an immunity/sensitivity to the ∂I/∂t problem and how they effect typical Superscalar architectures. The thrust of the research is focused in three areas: ∂I/∂ t high level noise models, architecture level solutions and instruction level solutions. |
