CMOS technology optimization for low voltage, low-power application

Due to the surging demand for hand held electronics products and the ever increasing power consumption by the high performance desk top applications, there is a growing interest in ways to reduce the power consumption of integrated circuits. Technology optimization has been studied as one of the effective methods to accomplish this. Such optimization includes the lowering of the threshold voltage for low voltage operation. Before the implementation of these low power technology approaches such as low threshold device technology on real products, several important questions have to be answered. These questions include: How is performance impacted as the supply voltage is dropped for lower power? What are the issues that determine the power-performance trade-off? How much help can technology optimization provide in this trade-off? In searching for the optimum operating point, what is an appropriate objective function? What are the optimized technology parameters at the optimum point of the trade-off? Can the resulting power-performance optimized devices be scaled into future technology generations? What are the most important issues in the fabrication of the power optimized MOSFETs? This work makes an attempt to address these questions. An analytical optimizer was built to reveal the principle device physics that determines the power-performance trade-off, to provide optimized technology parameters for the trade off, and to describe quantitatively the benefit of various levels of optimization. A scaling scenario results, which shows that the power optimized device can in theory be scaled into further technology generations. Various objective functions for low power optimization and their implication are also reviewed with the data extracted from fabricated devices. Sub quarter micron MOSFETs with optimized parameters were fabricated. The results support the theoretical prediction that these device are scalable and can reduce the power consumption significantly with little compromise in performance. Various device design and process techniques were also investigated theoretically, through analytical study and device simulation, and experimentally. Circuit techniques to handle the high leakage currents in standby mode in the optimized technology are also demonstrated.