Viscoelastic stress analysis and fatigue life prediction of a flip-chip-on-board electronic package

A rapidly growing method for attaching computer chips to substrates is flip-chip-on-board. Analytical models for determining stresses and strains in the constituent materials of the electronic package aid in the understanding of failure mechanisms and factors that affect lifetime. The development of such models is an important step in optimizing the design of flip chip packages. The framework for a model that incorporates underfill cure, underfill cure shrinkage, viscoelastic properties of the underfill, and viscoplastic properties of the solder has been developed.; The localized nature of material failure and the presence of stress concentration points in the package make a finite element model a logical choice for determining the stresses and strains in a flip chip package. A two dimensional, plane strain finite element model is described along with the material characterization needed to supply the model with the material properties of the underfill material.; Fatigue life predictions are made based on the amount of plastic work accumulated in the solder joint during thermal cycling. The use of the model is demonstrated by comparing the performance of two underfill materials with significantly different properties. The underfill material with the higher modulus and longer relaxation times has a longer predicted lifetime. The preliminary results of a validation experiment agree favorably with the fatigue life predictions made using the model.; Finite element runs of the curing process are also made to study the effect curing temperature has on the residual stresses in the package after curing. Simulations were run at two different cure temperatures for each material.