| In recent years integrated circuit power consumption has become one of the most important and critical performance specifications for a wide range of mobile, battery-operated devices. This dissertation addresses the significant power dissipation limitations imposed on a fully implantable wireless neural recording system in which power must be minimized to avoid cellular necrosis. Two core PLL circuits, the voltage-controlled oscillator (VCO) and multimodulus divider, have been developed in a 0.6-mum BiCMOS process technology with a power dissipation target of 4.5 mW with a typical output frequency of 915 MHz. To facilitate the development of a low power VCO, a novel integrated inductor design method is proposed to optimize inductors specifically for power dissipation. Such optimized inductors result in minimum operating currents up to 25 times lower than inductors optimized for Q . To validate the inductor optimization design procedure, a library of over 150 integrated inductors has been developed, fabricated, and measured. Several methods are proposed for extracting frequency-dependent impedance models for the inductors. The best procedure is robust to noisy data and smoothly interpolates the measurements to provide an accurate model that is not unduly sensitive to measurement errors. Finally, the true-single-phase clock (TSPC) dynamic logic family is used to implement a pulse-swallowing multimodulus divider that boasts a normalized performance metric of 5 muW/MHz which is better than other dividers, including dual modulus prescalers, at similar technology nodes. |
