Design of 5-MB/S fractional -N RF transmitter in 900 MHz ISM band using GMSK data modulation techniques

This dissertation focuses on the development of a chip with intended application for use in an implanted neural data telemetry system. The specific research foci include the modeling of noise in a Fractional-N (Frac-N) synthesizer and development of a 5 Mbps transmitter in 900 MHz ISM band using Frac-N Gaussian Minimum Shift Keying (GMSK) data modulation techniques.;Mathematical model is developed for calculating rms phase error and determining spurs in the output of Frac-N phase lock loop (PLL). The model describes noise contributions due to the charge pump (CP), the phase frequency detector (PFD), the loop filter, the voltage controlled oscillator (VCO), and the delta-sigma modulator (DSM). Models are presented for the effects of static CP gain mismatch, CP dynamic mismatch and PFD reset delay mismatch. A simple analytic expression shows the level of Delta Sigma sequence noise caused by static CP current mismatch. It is further shown that unequal rise time and fall time constants of the CP result in dynamic mismatch noise. Reset delay mismatch in PFD is shown to contribute significantly to close-in phase noise. The model takes into account the reduction in CP thermal and flicker noise due to the changing duty cycle of Frac-N CP. The model is therefore useful in characterizing the noise performance of Frac-N at the system-level and simplifying the design of fractional-N synthesizers and transmitters. Analytical and simulated results are compared and show good agreement with prior published data on Frac-N realizations.;The behavioral model of Frac-N PLL helped in the system level design of a 5 Mbps Frac-N GMSK data transmitter. The noise contributions of the PLL macros obtained from the system level design, aided in transistor level design of the macros of Frac-N PLL. In particular, careful attention was paid to the design of CP and PFD to minimize the in-band noise due to CP/PFD non-linearities. The minimization of the out-of-band phase noise was done through proper selection of the topology and the order of DSM.;The prototype Frac-N chip was designed in LSV, 0.18μm mixed-mode/RF CMOS process. The chip comprises of PFD, CP, on-chip filter, prescalar, and on-chip LC-VCO. For testing, the Frac-N IC was mounted on a custom built impedance controlled printed circuit board (PCB). The digital DSM and GMSK filter were realized in FPGA mounted on another evaluation board. This evaluation board was interfaced with the Frac-N PCB to provide the prescalar control signals from the FPGA to the Frac-N IC. The PLL loop bandwidth was set to 2.1 MHz to perform in-loop modulation. Measured results show MASH-12 Frac-N at 925 MHz with an in-band rms phase error of 0.84° over 2.25 MHz bandwidth and out-of-band rms phase error of 3.72°. These measured phase noise is in good correlation with the phase noise predicted by the behavioral model of Frac-N PLL.