| CMOS active pixel sensors (APS) have evolved to become the de-facto standard in today's imaging applications. Most of these sensors operate in the voltage domain, where the pixels output voltage signals. Current mode image sensors are ones that output current signals. They possess many advantages over voltage mode APS, such as high readout speed, low supply voltage, small pixel size, and convenient analog signal processing. However, the fixed pattern noise (FPN) of such sensors have been poor historically, which prevented their widespread use.;This dissertation presents several original contributions towards building a better current mode image sensor. The first is a current mode readout scheme using velocity saturated readout transistor. Its high linearity allows efficient FPN reduction by correcting both offset and gain mismatch among pixels. A triple sampling approach is proposed to implement the correction in hardware. The second is a current mode pixel addressing scheme, which helps pixel miniaturization by eliminating the pixel-level selection switch. The third is a current mode successive approximation ADC, which employs a sub-binary radix scheme for missing code calibration.;Four test chips are presented to validate the proposed designs. The experimental results compared the linearity of different readout modes, and illustrated the effectiveness of the FPN reduction. Also, various current binning modes were demonstrated. The functional operation of the proposed ADC was verified. The calibration scheme was implemented in software, which successfully removed missing codes in the sub-binary ADC. Sample images from the test chips showed, for the first time, promising image quality which narrows the gap between current and voltage mode imaging. |
