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Efficient adaptation of multiple microprocessor resources for energy reduction using dynamic optimizatio

Posted on:2006-08-13Degree:Ph.DType:Dissertation
University:The University of Texas at AustinCandidate:Hu, ShiwenFull Text:PDF
GTID:1458390008959002Subject:Electrical engineering
Abstract/Summary:
The continuing advances in VLSI technology have fueled dramatic performance gains for general-purpose microprocessor, but microprocessor energy consumption has been increasing substantially in the past decade. The steady increase of microprocessor energy consumption significantly affects circuit reliability, cooling and package costs, and battery life of embedded systems.;Adaptive microarchitectures are one of the commonly used techniques to dynamically identify configurations that are desirable from performance and power perspectives. By matching hardware resources to a program's runtime requirements, adaptive microarchitectures can effectively reduce energy with minimal performance loss. However, the task of searching for the most energy efficient configurations is complicated by configuration space explosion, which may considerably impair an adaptive microarchitecture's performance and energy efficiency.;This dissertation presents a hardware adaptation framework for efficient management of multiple configurable units, utilizing a dynamic optimization system's inherent capabilities of detecting and optimizing dominant code regions (hot spots). The framework uses hot spot boundaries for phase detection and hardware adaptation. Since hot spots are of variable sizes and are often nested, the framework can decouple the reconfiguration of CUs with diverse adaptation costs by adjusting the granularity of adaptation based on each CU's reconfiguration cost.;This dissertation also studies the interference imposed by one CU's configuration changes on others' adaptation. CUs with minimal mutual interference can be adapted in parallel. In addition, for some CUs, one's size reduction usually prompts the other to choose a smaller size for energy reduction. Hence, the search of those CUs' best configurations biases toward certain paths, and thus prunes the tuning space. Employing the tuning-reduction strategies, the proposed framework significantly improves the energy efficiency of an adaptive microarchitecture.;The energy and hardware adaptation impact of two important dynamic optimization services, JIT optimization and garbage collection, are also investigated in this work. By stressing the data caches, both dynamic optimization services decrease the average power dissipated by a dynamic optimization system. Furthermore, owing to their distinct runtime characteristics and their capabilities to alter program runtime behavior, the two dynamic optimization services change the adaptation preferences of configurable hardware units, and influence the energy efficiency of an adaptive microarchitecture.
Keywords/Search Tags:Energy, Adaptation, Dynamic, Microprocessor, Hardware, Adaptive, Reduction, Efficient
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