Non-linearity of LDMOS-based RF power amplifiers for wireless communications

In this work, the non-linearity of LDMOS-based power amplifiers was examined from both circuit and device physics levels. Two representative devices from Motorola (i.e., MRF183S and MRF21125) were used for commercial device model extractions. Large-signal model parameters were extracted using the nonlinear equation fitting procedures in Origin software. The values of other elements were decided using either DC sweeping or S-parameters optimizations. The nonlinear gate-drain capacitance Cgd was obtained from either the published datasheets or S-parameters optimizations. Based on this complete device equivalent circuit, Harmonic Balance analysis was extensively conducted in ADS for both the nonlinear Cgd case and the constant Cgd case (i.e., a control). Our results show that the nonlinear Cgd clipping phenomenon is the dominant factor in defining the overall performance (for example, a 1 dB gain compression point) of the power amplifiers. This Cgd clipping mechanism is supported by the fact that the transducer gain drops by 1 dB before the dynamic load-line contours reach the IV Knee clipping region while Cgd does clip severely. This is complementary to the traditional IV Knee-clipping gain roll-off mechanism. To further validate this new mechanism and accurately model this crucial nonlinear Cgd, a prototype device was designed. It was simulated using Silvaco and fabricated at Integral Technology, Inc. An in-depth analysis of this device supports the above statement.; Before deriving the Cgd model, physics-based interpretations of Motorola's MET capacitance model (an empirical model) were given using the analogy of the MESFET gate-drain capacitance. Modeling work based on Silvaco simulated data of the prototype device showed that Cgd could be separated into a channel component and a sidewall component. Subsequently, a modified pseudo-2D model and a cylindrical field model were proposed to model these two components respectively. The modeled data agreed with the Silvaco simulated data. Finally, the scaling guidelines for LDMOS design were given. Scaling down the gate electrode thickness was found to be an effective way to reduce Cgd. Silvaco simulations performed on devices with a smaller gate-electrode thickness validated our scaling guidelines.