Integrated Circuits and Systems for Sparse Signal Acquisition based on Asynchronous Sampling and Compressed Sensing

This dissertation builds on the recent theoretical and experimental work on asynchronous sampling and compressed sensing. Our goal is to exploit the advances in the theory to design practical data acquisition systems capable of directly acquiring sparse signals at sub-Nyquist rates. We focus specifically on increasing the power efficiency and decreasing the complexity of the signal acquisition process compared to existing conventional Nyquist rate solutions for biomedical sensor and wideband spectrum sensing applications.;The first half of the dissertation presents the design and implementation of an adaptive resolution asynchronous ADC which achieves data compression for sparse and burst like signals by the inherent signal dependent sampling rate of the asynchronous architecture. The main contribution of this work is the implementation of an adaptive resolution (AR) algorithm which varies the quantizer resolution of the ADC with the slope of the input signal, in order to overcome the tradeoff between dynamic range and input bandwidth typically seen in asynchronous ADCs. This allows the maximum possible input bandwidth to be achieved regardless of the dynamic range requirement. By reducing the quantizer resolution during periods of high input slope, further data compression is also achieved. A prototype ADC was fabricated in a 0.18microm CMOS technology and optimized for subthreshold operation in order to increase the power efficiency for low-frequency biomedical sensor applications. The prototype ADC achieves an equivalent maximum sampling rate of 50kS/s, an SNDR of 43.2dB, and consumes 25microW from a 0.7V supply. The ADC is also shown to provide data compression for accelerometer and ECG applications as a proof of concept demonstration.;The second half of this dissertation presents the design and implementation of a compressed sensing based analog-to-information converter (AIC) for wideband spectrum sensing applications. The core of the design is an ultra low power moderate rate ADC that randomly samples the received signal at sub-Nyquist rates. In order to ensure proper functionality with the random clock signal and to maximize power efficiency, a prototype edge-triggered charge-sharing SAR ADC core was implemented in 90nm CMOS technology. The prototype SAR ADC core achieves a maximum sample rate of 9.5MS/s, an ENOB of 9.3 bits, and consumes 550microW from a 1.2V supply. Measurement results of the compressed sensing AIC demonstrate effective sub-Nyquist random sampling and reconstruction of signals with sparse frequency support suitable for wideband spectrum sensing applications. When accounting for the increased input bandwidth compared to Nyquist, the AIC achieves an effective figure of merit (FOM) of 10.2fJ/conversion-step.