Real-Time Heterogeneous Video Transcoding for Low-Power Applications

In this dissertation, I have presented a high throughput, yet precise, MPEG-2 to H.264/AVC transcoding algorithm that achieves an average of 92.8% reduction in the required transcoding run-time at a price of an acceptable PSNR degradation, which nominates my transcoding solution for real-time video applications. In particular, the proposed accelerating MPEG-2 to H.264/AVC transcoding algorithm employs a novel Intra mode selection and direction prediction technique that utilizes the DCT coefficients directly from the MPEG-2 side of the transcoder for such purpose. The proposed Intra prediction methodology successfully decides the Intra macro-block mode, then predicts the corresponding reconstruction direction for the H.264/AVC encoder side of the transcoder in a completely Full-Search Free technique.;In fact, the H.264/AVC standard only documents the Intra mode decision and direction prediction process for the decoder version on the H.264/AVC codec. For such reason, I modified my transcoding Intra prediction algorithm to fit as an enhancement to the H.264/AVC standard decoder. For this purpose, also the properties of the DCT coefficients are employed to significantly reduce the overall run-time of the H.264/AVC standard decoder. Specifically, a high throughput early Intra mode decision and direction prediction algorithm is presented in the scope of this dissertation, which has been entitled "FSF Intra Prediction algorithm". The algorithm also utilizes the macro-block DCT coefficients directly from the output of the inverse quantization module for such purpose and before macro-blocks' samples get transformed back to the pixel domain.;The novelty of the proposed FSF algorithm is that it selects the macro-block Intra mode, then predicts the macro-block reconstruction direction not only fast, but also in a completely Full-Search Free environment. The experimental results show that the FSF Intra prediction software implementation achieves over 56% reduction in the Intra prediction run-time while preserving the same bit-rate and subjective quality as the standard H.264/AVC. However, the cost of the obtained run-time reduction is a negligible PSNR degradation of less than 0.72 dB when it is compared to the PSNR achieved by Intra prediction algorithm that currently employed by the H.264/AVC JM 18.2 reference software.;Moreover, I extended my work by introducing the low-power hardware architecture design for the proposed high-throughput FSF Intra prediction algorithm. Furthermore, both FPGA prototype and ASIC chip design and implementation are developed for the proposed FSF Intra prediction hardware architecture. In closing, the proposed 45 nm ASIC design achieves a stable operating frequency of 140 MHz, which strongly nominates the FSF Intra prediction hardware design for real-time H.264/AVC video devices. Even more, the total power consumption of the ASCI design was only 9.1 mW, which qualifies my chip design for low-power mobile video applications.