Noise in Large-Signal, Time-Varying RF CMOS Circuits: Theory & Design

RF CMOS design is now a mature field and CMOS radio transceivers have become standard in most consumer wireless devices. Like any wireless RF design, at the heart of the endeavor is the requirement to frequency translate signals between baseband and RF with minimal introduction of noise and distortion. This translation is generally accomplished using time-varying, strongly nonlinear circuits, whose operation and noise performance cannot be understood using standard LTI circuit analysis techniques. This work seeks to address some of the design and analysis challenges posed by a variety of these non-linear, time-varying CMOS RF circuits, specifically in the context of low noise design.;First, a new wideband receiver architecture is proposed and analyzed. Using two separate passive-mixer-based down-conversion paths, noise cancelling is enabled, but voltage gain is avoided at unwanted blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation.;Second, using a phasor-based analysis method, new theoretical results relating to noise mechanisms in LC oscillators are described. Amplitude noise and Q-degradation is quantified for the first time, while the analysis method is also used to re-derive a fundamental limit to the achievable phase noise of any LC oscillator.;Finally, a low-noise, wideband PLL is described that is suitable for emerging mm-wave standards. This design demonstrates that CMOS technology is capable of delivering a high-performance wideband VCO, even at mm-wave frequencies.