A variation aware resilient framework for post-silicon delay validation of high performance circuits

Despite advances in design and verification, it is becoming increasingly common for high-performance designs to misbehave on silicon. This is due to performance issues, such as, timing bugs, which cause significant percentage of fabricated chips to have delay failures that are first discovered only during post-silicon validation. Delay marginality is one such important variation induced timing bug that is often missed by existing validation approaches, as it changes delay to produce errors in significant fraction of fabricated chips, even in the absence of defects and even when the variations in the fabrication process are within the normally expected levels, i.e., even when there is no abnormal process drift. Thus, it becomes imperative to improve quality of validation with respect to delay marginalities.;One obvious approach to achieve this would have been to adapt and apply the existing delay testing approaches (where the generated vectors are applied to a fabricated copy of chip to measure delay) to generate vectors for delay validation, i.e., vectors that are guaranteed to expose all the delay marginalities. But, several recent case studies using fabricated chips show that existing path delay testing approaches generate vectors that fail to expose the delay marginalities on silicon. The primary reason for such an anomaly can be attributed to the inability of existing approaches to account for the effect of advanced delay phenomena such as Multiple Input Switching (MIS) and process variations on delay. This necessitates the development of a variation aware framework that can provide an accurate estimate of the post-silicon delay.;The goal of this dissertation is to develop new models and methodologies to accurately estimate the delay of any given fabricated copy of a design. We identify key strengths of validation and formulate our problem of discovering delay marginalities. We also identify the major phenomena affecting gate delay namely Multiple Input Switching (MIS) and successfully develop new models (based on a new notion of bounding approximations) and methods that account for inaccuracies and variability at practical run-time complexities and are suitable for both pre- and post-silicon timing tasks. We show that compared to existing delay models, our delay models are much more accurate and provide order of magnitude reductions in runtime. Subsequently, we adapt and significantly extend existing delay testing approaches to generate vectors for delay validation, i.e., vectors that are guaranteed to detect the worst-case delay for a significant fraction (within a user-specified validation budget) of fabricated chips. We show that our vectors, being MIS and variation aware, invoke much higher delay than vectors generated by existing vector generation approaches. Finally, we developed a variability aware divide and conquer based method for efficient post-silicon validation that gives substantial reduction in test-application time and hence the test-cost. Our experimental results demonstrate that we have developed the first variation aware resilient framework for post-silicon delay validation..