| A methodology is developed to realize a generalized class of fractional-order transfer functions in digital hardware using a low-cost field programmable gate array (FPGA) device. A systematic approach is first developed to implement fractional-order integrators and differentiators in fixed-point hardware, wherein each coefficient and signal is represented with a custom number of bits. Each fractional-order operator is implemented as a set of first-order sections in parallel in both shift-form and delta-form structures. Use of the delta form is found to save 25% in total data bits required for the coefficients and state variables compared to the shift-form realizations for three examples, which include two integrators and one differentiator.;A generalized class of fractional-order transfer functions is then implemented in digital hardware using the fractional-order operators as building blocks. Different realization structures, including the partitioned form, the integral feedback form, and the derivative feedback form, are exploited to construct the fractional-order systems. From three illustrative example systems, the integral feedback form is shown to be the most effective structure. The unique feature of the developed methodology is that it allows for changes to a fractional-order system to be made by simple substitutions of individual fractional-order blocks rather than a redesign of the entire approximation; the resulting realization is accurate, efficient, and economical in terms of cost and time investment. |
