| This dissertation presents circuit and system innovations in the design of Ferroelectric Random Access Memory (FeRAM) and in the design of an area-efficient and power-aware cryptography processor for smart cards and portable electronic devices.; A novel read scheme is proposed that reduces FeRAM's read access time by 40% compared to FeRAM's conventional read scheme. This has been achieved by relying on the capacitance difference of the cell capacitors storing a "1" and a "0", as opposed to relying on their charge difference. In addition to reducing the read access time, the proposed read scheme relieves the constraints on the bitline size imposed by other read schemes. This, in turn, makes it feasible to use FeRAM in applications such as nonvolatile FPGA, where small memory blocks with short bitlines are required. The performance of the proposed read scheme is verified by circuit analysis, simulation results, and the measurement results of a test chip implemented in 0.35mum CMOS+Ferro technology.; We have used the FeRAM in the design and implementation of a proposed universal cryptography processor for smart cards. The proposed architecture utilizes a microcoded control unit and a reconfigurable ALU to perform three standard cryptography algorithms: two private-key (DES, AES) and one public-key (ECC). Exploiting the Optimal Normal Basis (ONB) representation of the field elements for ECC, the implemented SRAM-version of the processor in 0.18mum generic CMOS technology occupies 2.25mm2 (only 9% of total ISO 7816 smart card chip-area), provides the standard throughput of 874.5kbps, and in low power mode consumes 1.32mW at 1.1 V power supply and 3.34MHz clock frequency. The FeRAM-version of the cryptography processor provides nonvolatile configuration bits that are changed only to invoke an algorithm change. |
