Gyrator-based synthesis of active inductances and their applications in radio-frequency integrated circuits

The unavailability of high-quality integrable inductors that are small, stable, tunable, and inexpensive, is a fundamental limitation of today's monolithic fabrication processes. Planar spirals of metallization are commonly used to synthesize on-chip inductances, but these structures offer low quality factors (or "Q"s) and are neither small nor implicitly tunable. Compared to passive inductors, active realizations consume much less die area, have inductance values that can be easily tuned, and are capable of producing extremely high Qs. Active topologies based on the gyrator and implemented with transconductance amplifiers perform the best at high frequencies, but can suffer from instability for designs that require both high Qand high-frequency operation.; To better understand the inherent design trade-offs between circuit stability, frequency response, Q, and the frequency at which Q is maximum, a detailed stability analysis of gyrator-based active inductors using transconductance amplifiers is performed. Design equations and operating constraints are derived to control the circuit damping and produce inductance values that are nearly independent of frequency over the required operational frequency range.; The results of the stability analyses are used to design a suite of six cascode gyrator inductors with nominal inductance values from 1.3-14.3 nH and tuning ranges from +/- 22% to +/- 35%. The wide tuning ranges enable the suite of inductors to produce any inductance between 0.88-18.2 nH. Quality factors range from 10-60,000 and inductances are within +/- 7-8% of their respective nominal values for signal frequencies between 800 MHz and 2 GHz using SPICE transistor parameters for a standard silicon CMOS process. Power consumption ranges from 1.7-18.6 mW using a single 2.5 V supply, and die areas vary from 16 to 543 times smaller than those required of comparable spiral inductors.; Though the synthesized inductances use transistor models from a 0.13 mum CMOS process, the shortest channel length used in any design is 0.28 mum. All designs, therefore, can easily be ported to less expensive processes.; One inductor from the suite is used in two signal processing applications with excellent results, illustrating the practicality of the final designs.