| We propose a novel approach to the analysis and design of reliable power distribution networks for digital VLSI circuits. The optimized power and ground buses should meet or outperform the noise level specifications while achieving minimum die size. The flow consists of two main steps: analysis and optimization. During the analysis phase, the power and ground buses are broken down into multilevel hierarchical structures. Different algorithms are employed for the analysis at different hierarchies. In all the analyses, input-independent algorithms are used to reduce simulation time and obtain an accurate noise upper bound. Additional techniques (namely, sensitivity analysis, constraint graph optimization, and reduced order modeling techniques) are also employed to improve the accuracy with little overhead in terms of the simulation time. An algorithm is developed to determine the conditions that will cause maximum delay along target critical paths with power/ground bus voltage variation effects. Finally, new techniques for decoupling capacitance placement and power grid area optimization are presented. |
