| Optical projection lithography, currently employing deep-ultraviolet radiation, is the most advanced technology used in the silicon integrated circuit industry for the high-volume manufacturing of semiconductor devices. Scaling-down the dimensions of the feature sizes is a key to fabricating more powerful and cost-effective devices. It is a primary technological trend in microlithography as well as one of the persistent goals in chip fabrication. For miniaturization of the feature size in microchips, continued improvements in optical lithography have focused on the exposure tool on the basis of scaling Rayleigh's equation, i.e., decreasing the lithographic resolution and/or increasing the depth of focus. This fact drives the development of imaging light sources with shorter wavelengths. On the other hand, optical lithography is rapidly approaching technical limitations for imaging much finer features.; Continued efforts to reduce the minimum feature size for increased chip performance (while faced with the limitations on the optical system) bring about the development of various resist processing methods for contact patterns. This research focused on contact-hole processing using thermal reflow at hardbake. It is a technique for size reduction of the contact hole which utilizes recyclable/reversible thermal characteristics of polymer-based resists. Hardbake is one of the lithography processing steps, which is completely independent of current and near-term lithographic exposure tools. It includes a desirable thermal reflow that accompanies significant size reduction of the contact hole under specific bake process conditions. Resist thermal reflow is driven by thermal transitions, which largely consist of solid and viscous, through material relaxation with both temperature and time dependence during thermal cycling at hardbake.; Through thermal transitions in the resist reflow process, recognizable dimensional changes of the contact hole are strongly affected by the primary temperature-dependent material properties, bake cycle parameters, contact-hole dimensions, and the type of contact array. This was identified with two comprehensive finite element models, i.e., thermal and structural, that were developed to simulate the conventional bake process. Parametric studies were performed to quantify relative effects of the influential system parameters, either directly or indirectly, on the resist contact-hole profile for the bake cycle profile simulated. |
