Conductive trace design in three-dimensional circuit architectures: Heat transfer analysis and experiments

Recent research efforts have been devoted to developing technologies for fabricating electronic circuits in three dimensions using ink jet processes. The management of generated heat in such circuits is expected to be a critically important issue in their operation, which will require them to incorporate specialized design features for promoting the removal of unwanted heat from key areas and the limiting of component temperatures to safe levels. Hence, effective tools for predicting the heat transfer characteristics of three-dimensional circuits are required in order to develop optimum designs for such circuitry.;This research encompasses a course of investigation including the development of such design tools and their verification using experimental methods. These experimental methods consisted of thermal tests conducted with a variety of prototype circuits constructed in three dimensions, with materials appropriate to the overarching design concept.;After the verification process, the investigation proceeded with the construction of numerical models intended to comparatively assess the effectiveness of a range of design features proposed for application in the design concept. These features included specialized extensions to the conductive traces expected to enhance passive heat rejection, and thereby to limit the observed temperature rise in the discrete resistive component. The relative impact of each of these structures is comparatively evaluated using the developed tools. It is observed that the presence of these specialized structures do act to limit the observed temperature rise. However, the specifics of the basic conductive trace design, namely the choice of material and the thickness of the trace, have by far the greater effect on the heat rejection from the discrete resistor and hence a much larger impact on the peak temperature rise.;Further research centered on the fabrication and testing of a circuit which more fully incorporated the 3-D architecture by employing a surface-mount technology (SMT) resistor and by embedding the resistor and conductive components within a cast polymer matrix. Experiments with this circuit and corresponding finite-element models showed that for the power dissipation levels investigated, the presence of the embedding medium actually results in lower temperatures at the resistive component.;It was also shown that, in terms of convection modeling, film coefficients calculated by standard methods do not effectively account for interactions between adjacent convection surfaces of these circuit architectures, giving numerical temperature results which correlated poorly with live test data. It was further shown that a numerical model featuring thermal/fluid dynamics capability and simplified geometry compared to the actual circuit can give resistor temperature results which compare very well to the live tests. Taking the thermal/fluid model results as a data source, improved values for the film coefficients can be calculated and applied to models not featuring fluid capability. The models with improved film coefficients similarly provided resistor temperature values which correlated well with the live test results.