| As 90nm process technology starts to merge into the mainstream manufacture of high-end ICs, and manufacturing process variations increase, the demand for high-quality Electrical Design Automation (EDA) tools, especially defect-diagnosis tools, grows dramatically.; The purpose of defect diagnosis is to determine the cause of failure in a manufactured, faulty chip. A good diagnostic tool should effectively assist a designer in quickly and accurately locating the failure. The quality of a diagnosis impacts directly the time-to-market and the total product cost.; This dissertation consists of four parts. In the first part, we present a multiple-fault-diagnosis methodology. Two algorithms are proposed to enhance the diagnosis efficiency. Also n-detection tests are used to further improve the diagnosability. In the second part, we first describe the proposed graph-based circuit representation; then we analyze the multiple-fault diagnosis problem in depth and propose our diagnosis algorithm. To improve the applicability of our algorithm, an efficient heuristic is proposed by utilizing layout information. In the third part, we explain how we utilized circuit timing information. Also we have proposed a simulation-based technique to significantly improve the diagnostic resolution for at-speed related defects. In the last part, we proposed a methodology to deal with the hold-time defects that occur at the data path. |
