| Multi-core chips are now commonplace in server, desktop, and even embedded systems; however, these chips create an inflection point for mainstream software development. To benefit from the additional performance offered by multiple cores, application developers have to develop parallel programs and deal with cumbersome issues such as synchronization tradeoffs and deadlock avoidance. In this setting, Transactional Memory (TM) has surfaced as a promising technique to simplify shared-memory parallel programming.;Recent years have seen the proposals of several different TM systems; however, most TM systems have been evaluated using microbenchmarks, which may not be representative of any real-world behavior, or individual applications, which do not stress a wide range of execution scenarios. To address this problem, I introduce the Stanford Transactional Applications for Multi-Processing (STAMP), the first comprehensive benchmark suite for evaluating TM systems. STAMP consists of eight benchmarks and represents several application domains, covers a wide range of transactional execution cases, and ports easily to many types of TM systems.;Using STAMP, I evaluate TM implementations based on hardware (HTM) and software (STM), and propose Signature-accelerated Transactional Memory (SigTM), a new hybrid TM system that combines the advantages of HTM and STM. SigTM uses small hardware signatures to accelerate the execution of software transactions, and thus presents a high-performance, flexible, and low-cost design. Moreover, SigTM is the first hybrid TM system to provide semantic guarantees between transactional and non-transactional code blocks. |
