Novel processes and structures for low temperature fabrication of integrated circuit devices

Low temperature fabrication of integrated circuit (IC) devices is important for large-area electronics and 3-D integration with CMOS electronics. This work addresses novel processes and transistor structures for these applications.;Polycrystalline silicon thin film transistors (poly-Si TFTs) are the highest performing devices for flat panel displays such as active matrix liquid crystal displays. Though the poly-Si TFT market share in the flat panel display industry is growing, realizing system-on-panel (SOP) products with all electronic circuitry directly fabricated on the display substrate requires improved device uniformity and reliability.;Two new processes are investigated to improve the performance, uniformity and reliability of poly-Si TFTs. The first is an ultra-low-temperature ultraviolet (UV) oxidation process with a maximum substrate temperature of 150°C developed for fabrication of poly-Si TFTs on flexible substrates. The UV oxide interfacial layer with a gate oxide deposited by PECVD shows excellent gate oxide characteristics for poly-Si TFT technology. Next, a defect passivation technique by selenium ion implantation into the TFT channel is shown to successfully passivate defects and improve TFT reliability under hot carrier bias conditions.;An alternative TFT design is examined, the accumulation-mode TFT. The accumulation-mode TFT employs a moderately-doped channel (∼ 10 18cm-3) of the same dopant type as the source and drain regions. Using a 2-dimensional device simulator, it is shown that this device can achieve good electrical characteristics, with thin gate oxide and silicon channel film thickness. Simulations for a single grain boundary in the TFT channel show that the accumulation-mode design is less sensitive to the grain boundary location as compared to a conventional enhancement-mode design.;A novel device, the poly-Si tunneling field effect transistor (TFET), is fabricated with a maximum process temperature of 600°C. The short channel TFETs exhibit enhanced on-state current mostly due to carrier multiplication by impact ionization, at a trade-off of high leakage currents. An optimal TFET device design is proposed to decrease the off-state current levels.;Several low-thermal-budget materials are investigated as candidate structural MEMS materials for 3-D integration with CMOS circuitry. The mechanical properties of four metals (Al, Ti, TiN and Ni) are extracted. Of the four, only Al exhibited a low average tensile stress suitable for MEMS applications, but it had large strain gradient. Poly-Si formed by aluminum-induced-crystallization (AIC) at a maximum temperature of 350°C showed improved mechanical properties (low compressive stress and moderate strain gradient). An additional excimer laser anneal (ELA) at low laser fluence of 100 mJcm2 yields superior mechanical properties so that AIC poly-Si is suitable for integrated MEMS applications such as inertial sensors and hybrid relay/CMOS circuits.