Characterization of floating gate implantation dose and its effect on PMOS Electrical Erasable Cell (PEEC) memory arrays

In many System on Chip (SoC) applications, it is desirable to store code and data in a non-volatile memory (NVM) to maintain the state of the system even in the power-off mode. The most flexible solution is to embed a Flash Electrical Erasable Programmable Read Only Memory (EEPROM) into the SoC, in which small blocks of non-volatile memory can be erased and re-written if a change to the data or code is required. This also enables in-system programming of the SoC. This work deals with the reliability improvement for a unique type of memory cell, namely, the P-type Metal Oxide Semiconductor (PMOS) EEPROM Cell PEEC. One major component of the PEEC array corresponding to the work of this dissertation paper is primarily based on the fact that when polysilicon2 overlaps polysilicon1, it creates a particular thin film called polysilicon1 side-wall oxide, which consequently affects several device characteristics such as endurance, retention and coupling ratio. This research explores different processing techniques geared toward improving the electrical performance of polysilicon1 side-wall oxides. The main aspects for optimizing cell performance were the polysilicon1 implantation dose as well as the bottom oxide component of the interpolysilicon oxide. The PEEC memory array was successfully made when the floating gate received a 5000 trillion per centimeter square implanted phosphorous atoms and the bottom oxide was changed to high temperature oxide (HTO). The process was successfully incorporated into manufacturing and resulted in at least 1 million erase-write cycles of endurance and over 1008 hours of retention. The memory cell is currently serving a large amount of real applications.