Optimizing voltage gain, thermal noise, and settling time of CMOS operational amplifiers by using moderate inversion

Complementary metal-oxide silicon (CMOS) amplifiers used in switched capacitor circuits require high voltage gain, low input-referred thermal-noise voltage, and fast settling time. This dissertation presents optimization techniques for two types of CMOS amplifiers. The first amplifier is a two-stage, Miller-compensated, low-voltage amplifier. As the CMOS transistor size and power supply voltage for integrated circuits continue to decrease, the two-stage amplifier with folded-cascode first stage is a good choice for high gain, wide bandwidth, and low voltage operation. This dissertation presents a new optimization method that uses the CMOS transistor inversion level and moderate-inversion operation for selected devices. This achieves required performance while saving about 37% in power consumption compared to existing strong-inversion designs. The second amplifier presented is a gain-boosted, single-stage amplifier. This amplifier has high voltage gain and improved frequency and transient performance at lower power consumption compared to two-stage amplifiers. This dissertation investigates the frequency response of the internal gain boosting amplifier and describes a new compensation method to improve the amplifier frequency response. This saves about 70% in power consumption for the internal gain boosting amplifier compared to existing designs. Finally, this dissertation presents the use of low flicker noise CMOS amplifiers for continuous-time, sigma-delta modulators in analog-to-digital converters (ADCs) used for wireless biomedical sensing applications.