| CPU manufactures are trending toward designs with multiple cores on a chip in order to continue to scale with technology. One common feature of these multicore chips is resource sharing among sibling cores that sit on the same chip, such as shared last level cache and memory bandwidth. Without careful management, such sharing could open a loophole in terms of performance, fairness, and security concerns.;My dissertation addresses resource management issues on multicore chips at the operating system level. Specifically, I introduce three techniques to control resource usage and study a variety of resource management policies that consider fairness, quality of service, performance, or power.;First, I propose a hot-page coloring approach that enforces cache partitioning on only a small set of frequently accessed (or hot) pages to segregate most inter- thread cache conflicts. Cache colors are allocated using miss ratio curves. The cost of identifying hot pages online is reduced by leveraging knowledge of spatial locality during a page table scan of access hits. Hotness-based page coloring greatly alleviates the disadvantages of naive page coloring (memory allocation constraint and recoloring overhead) in practice.;Second, I demonstrate that resource-aware scheduling on multicore-based SMP platforms can mitigate resource contention. Resource-aware scheduling employs a simple heuristic that can be easily derived from hardware performance counters. By grouping applications with similar memory access behaviors, resource contention can be reduced and better overall system performance can be achieved. Aside from the benefits of reduced hardware resource contention, it also provides opportunities for CPU power savings and thermal reduction.;Finally, I show how to reuse existing hardware features to control resource usage. I demonstrate it online a hardware execution throttling (e.g. , voltage/frequency scaling, duty-cycle modulation, and cache prefetcher adjustment) based framework to effectively control shared resource usage (regardless of resource type) on multicore chips. |
