Analysis and design of on-chip phase noise measurement modules

An on-chip phase noise measurement module is presented. Unlike previously published monolithic measurement techniques that measure jitter in the time domain, the proposed circuit measures phase noise spectrum. The phase noise measurement module is fully integrated and does not require a spectrally clean reference clock or external calibration. The module can be integrated as part of a Built-In Self Test (BIST) scheme to characterize the close-in noise performance of Phase Locked Loops (PLLs) and Clock-Data Recovery (CDR) circuits. The proposed circuit uses a low-noise Voltage Controlled Delay-Line (VCDL) and mixer-based frequency discriminator to extract the phase noise fluctuations at baseband. The VCDL is used to convert the signal's frequency fluctuations into phase fluctuations; which are then converted by a mixer into voltage fluctuations. The signal is then processed through a combined Baseband LNA (BBLNA) and Low-Pass Filter (LPF) stage and either sent directly off-chip in analog form or sampled and digitized using an Analog-to-Digital Converter (ADC). A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point eliminating the impact of Process, Voltage and Temperature (PVT) variations on the measurement accuracy. The proposed circuit is fabricated using a 0.25 um digital CMOS process and operates up to a 2 GHz carrier frequency. Experimental results show that the measurement module has a Single Tone (ST) measurement sensitivity of -75 dBc and an equivalent phase noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.