Efficient digital baseband predistortion for modern wireless handsets

One of the major challenges in modern wireless transceiver design stems from the fundamental trade-off between the linearity and power efficiency of RF amplifiers. On one hand, the varying envelope of spectrally-efficient modulated signals such as wideband code division multiple access (WCDMA) and orthogonal frequency division multiplexing (OFDM) interacts with the amplifier nonlinearity, resulting in both in-band distortion and undesired out-of-band spectral regrowth. These distortions cause the violation of the strict standard requirements. On the other hand, improving the inherently low power efficiency of amplifiers generates significant savings in cooling and running costs at the base station infrastructure and enables an equally important increase in mobile handsets battery life.;Digital baseband predistortion is one of the most effective techniques used to reconcile the conflicting requirements of power efficiency and increased data throughput per unit bandwidth. The accuracy and flexibility of digital predistortion allows the use of a highly nonlinear amplifier to increase the overall power efficiency while meeting the strict performance requirements.;This dissertation studies the design of an efficient adaptive digital baseband predistorter for modern cellular handsets that combines low power consumption, low implementation complexity, and high performance. The proposed enhancements are optimized for hardware implementation.;We first present a thorough study of the optimal spacing of linearly-interpolated lookup tables supported by theoretical calculations as well as extensive simulation experiments. A constant-SNR compander that increases the LUT predistorter's supported input dynamic range is derived. A corresponding low-complexity approximation that lends itself to efficient hardware design is also implemented in VHDL and synthesized with the SYNOPSYS DESIGN C OMPILER. This dissertation also proposes an LMS-based predistorter adaptation that is optimized for hardware implementation and compares the effectiveness of the direct and indirect learning architectures.;Analog RF imperfections such as quadrature imbalances and varying antenna impedance during the device operation severely reduce the effectiveness of adaptive predistorters. A novel predistorter design with quadrature imbalance correction capability is developed and a corresponding adaptation scheme is proposed. This robust predistorter configuration is designed by combining linearization and I/Q imbalance correction into a single function with the same computational complexity as the widespread complex-gain predistorter. An adaptive gain and phase normalization technique that reuses the predistorter update hardware is also proposed to mitigate the effects of varying antenna matching condition during predistorter adaptation.