Effect of Ion Flux (Dose Rate) in Source-Drain Extension Ion Implantation for 10-nm Node FinFET and Beyond on 300/450mm Platform

The improvement of wafer equipment productivity has been a continuous effort of the semiconductor industry. Higher productivity implies lower product price, which economically drives more demand from the market. This is desired by the semiconductor manufacturing industry. By raising the ion beam current of the ion implanter for 300/450mm platforms, it is possible to increase the throughput of the ion implanter. The resulting dose rate can be comparable to the performance of conventional ion implanters or higher, depending on beam current and beam size. Thus, effects caused by higher dose rate must be investigated further. One of the major applications of ion implantation (I/I) is source-drain extension (SDE) I/I for the silicon FinFET device. This study investigated the dose rate effects on the material properties and device performance of the 10-nm node silicon FinFET. In order to gain better understanding of the dose rate effects, the dose rate study is based on Synopsys Technology CAD (TCAD) process and device simulations that are calibrated and validated using available structural silicon fin samples.;We have successfully shown that the kinetic monte carlo (KMC) I/I simulation can precisely model both the silicon amorphization and the arsenic distribution in the fin by comparing the KMC simulation results with TEM images. The results of the KMC I/I simulation show that at high dose rate more activated arsenic dopants were in the source-drain extension (SDE) region. This finding matches with the increased silicon amorphization caused by the high dose-rate I/I, given that the arsenic atoms could be more easily activated by the solid phase epitaxial regrowth process. This increased silicon amorphization led to not only higher arsenic activation near the spacer edge, but also less arsenic atoms straggling into the channel. Hence, it is possible to improve the throughput of the ion implanter when the dopants are implanted at high dose rate if the same doping level with a lower wafer dose can be achieved. In addition, the leakage current might also be reduced due to less undesired dopants in the channel.;However, the twin defects from the problematic Si{111} recrystallization is well-known to cause excessive leakage current to the FinFET. This drawback can offset the benefits of the high dose rate I/I mentioned above. This work produced the first attempt at simulating the electrical impact of twin defects on advanced-node (10 nm) FinFET device performance. It was found that the high dose-rate I/I causes more twin defects in the silicon fin, and the physical locations of these defects were close to the channel. The defects undesirably induced trap-assisted band-to-band tunneling near the drain, which increased the leakage current. This issue could be mitigated by using asymmetrical gate overlap/underlap design or thicker spacer for SDE I/I so that the twin defects are not located in the depletion region near the drain.