Nanoscale device and circuit characterization, modeling, reliability and failure analysis

This dissertation presents an overview of the Nanoscale technology scaling trends and challenges, and focuses on the device characterization, device modeling, reliability analysis, and failure analysis of devices in Nanoscale regime.; Nanoscale MOSFETs are characterized electrically with Charge-Pumping (CP), Linear Voltage Ramp (LVR), Current-Voltage (I-V), Capacitance-Voltage (C-V), and subthreshold-slope techniques. A three-subband quantum mechanical mobility model is developed for high-K/SiO2 systems, which considers both surface roughness and Coulomb scattering effects. The influence of quantum effects on the surface potential, the inversion layer carrier density, surface roughness mobility and Coulomb scattering mobility in the inversion layer are studied.; Carrier transport is modeled in nanoscale MOSFETs with the development of a physics-based, 2-D, three-subband quantum-mechanical model based on ballistic carrier transport and quantum-mechanical transport, which considers gate voltage drain current dependence of inversion layer electron density, surface potential, and thermal injection velocity.; High dielectric constant (high-K) gate dielectric materials are introduced to reduce the gate tunneling current while keeping the same equivalent electrical thickness. An accurate direct tunneling modeling is critical to understand the scaling limits. In our work, we develop a physics-based, three-subband quantum-mechanical models based on Poisson-Schrodinger equations and a direct tunneling model based on the WKB approximation to calculate the inversion layer charge density to model the gate leakage current for ultra-thin SiO2 and several different high-K gate dielectrics. The effects of effective oxide thickness (EOT), dielectric constant and barrier height on the direct tunneling current are studied as a function of gate voltage. The scaling limits of high-K gate dielectrics are explored.; The dissertation addresses various Failure Analysis (FA) challenges, reliability issues, and failure modes for Cu/low-K technology. The reliability analysis is demonstrated for gate dielectric integrity and integration of Cu and low-K dielectric. Finally we discuss the development and detailed characterization of several front-side and backside failure analysis techniques for copper, low-K and Silicon on Insulator (SOI) devices including reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP), wet chemical etching and combinations of these techniques.