Leakage power analysis and optimization in deep -submicron technologies under process variation

Technology scaling has taken circuit performance to unprecedented levels in the deep submicron regime. Although, each technology generation brings about great improvements in circuit density and performance, there is also a tremendous accompanying increase in power consumption. With portable electronics becoming the focus of the semiconductor industry, power has increasingly become a major consideration for circuit designers. Up to the 0.25 mum technology generation, power consumption was dominated by switching power. However, aggressive scaling of gate length has led to a strong rise in subthreshold leakage power consumption. Over the last few technology generations, leakage has become an increasingly significant proportion of the total power. At the 65nm node, the contribution of leakage power is projected to reach 54% of the total power, and is expected to grow with each technology generation. Leakage power analysis and reduction is an actively researched field, with various techniques approaching this problem from various different aspects. This dissertation primarily deals with analyzing the impact of threshold voltage and gate-length on leakage and approaches analysis and optimization techniques at the device, cell and design level.;At the device level, we analyze lithographic imperfections and their impact on device leakage. We also propose a method to utilize non-uniform lithographic patterns to create devices that have better delay and leakage characteristics than standard rectangular devices.;At the cell-level we propose standard-cell enhancement techniques involving multiple gate length assignment. We discuss a scheme for creating an enhanced standardcell library by assigning different gate lengths to different devices in a cell. The enhanced library can be used by a circuit optimizer for leakage and variability reduction.;Finally we propose design optimization methods to accurately and efficiently perform sizing, threshold voltage and gate length assignment simultaneously. We also propose transistor-level static timing and power analysis methods for power optimization of custom circuits.;In summary, this dissertation highlights the need to accurately analyze and optimize leakage power in the deep-submicron regime. It proposes several approaches towards the goal of supporting technology scaling, allowing designers and process engineers to continue improving circuit performance and density, without increasing power-limited yield loss.