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Thermal effects on VLSI circuits and microarchitecture

Posted on:2008-02-04Degree:Ph.DType:Dissertation
University:Northwestern UniversityCandidate:Ku, Ja ChunFull Text:PDF
GTID:1442390005469896Subject:Engineering
Abstract/Summary:
As technology moves into deep submicron and nanoscale era, undesirable trends such as increasing power density, leakage power, and temperature variation within chips have made thermal effects emerge as a major bottleneck in further technology scaling. Thermal effects are no longer considered as just a reliability issue, but it also has become a fundamentally important and comprehensive problem that includes timing and power issues as well. Therefore, thermal effects have to be an integral part of design and analysis of VLSI circuits and microarchitecture in nanoscale technologies.; In this dissertation, several thermal-aware design and analysis methodologies are presented. It is shown that the use of minimum area does not result in the minimum power and/or delay in nanoscale technologies due to thermal effects, and in some cases, may result in thermal runaway. A methodology using area as a design parameter to reduce the leakage power, and prevent thermal runaway is described. Then, various thermal-aware power reduction techniques for both RAM-tag caches in high-performance processors and highly-associative CAM-tag caches in embedded processors are introduced. Furthermore, a thermal-aware methodology for low-power repeater insertion that includes the electrothermal coupling effects between leakage power, temperature, and delay is presented. It is shown in this dissertation that thermal effects have to be an integral part of estimating the effectiveness of power reduction techniques in nanoscale technologies due to increasing leakage power, and its inclusion always results in higher reduction in power than conventional estimations. Moreover, it is shown that the temperature dependencies of the carrier mobility and the saturation velocity need to be treated separately when modeling the on-current, and a new compact and accurate model for CMOS circuit delay is introduced. Lastly, the scaling trends of temperature-dependent effects such as transistor on-resistance and leakage power are analyzed, and their impact on design methodologies is also studied. Many experimental results are also presented throughout the dissertation in support of the presented techniques and theory.
Keywords/Search Tags:Thermal effects, Power, Presented, Nanoscale
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