Nanoscale heat conduction in semiconductor devices and interconnects

It is well recognized that the high power densities and consequently the elevated temperatures in advanced microprocessors has emerged as a technological roadblock of nanoscale electronics. Based on the Technology roadmap (ITRS) predictions, continuous miniaturization of microelectronic devices and interconnects will lead to even larger heat dissipation, in particular in SOI, FinFET and Strained-Si devices and copper interconnects that are made from semiconducting or metallic layers of thicknesses in the order of 10--50 nm. A better understanding of the energy transport at nanoscales requires both simulations and experimental data on thermal transport properties of nanostructures, which are not widely available at the present time.; This work provides the experimental data and models for temperature-dependent (20K--450 K) thermal conductivities of pure and doped silicon layers of sub-100nm thickness doped with boron, arsenic and phosphorus impurities to concentrations in the order of 1020 atoms/cm3. Steady-state Joule heating and electrical-resistance thermometry in suspended structures are used for thermal characterization of silicon and copper layers. In addition, underlying physics and fundamentals of heat transport at nanoscale as well as diagnostic tools and experimental techniques for thermal characterization and thermometry of the nanostructures are discussed.; The experimental data for thermal conductivity of pure and heavily doped ultra-thin (20nm--100nm) silicon layers are smaller than the corresponding bulk values. The thermal conductivity reductions due to the phonon-boundary and---impurity scattering can be as large as one to two orders of magnitude depending on the temperature, thickness and; impurity type and concentrations. It is shown that neglecting the ballistic heat conduction effect results in nearly 300% error in estimation of thermal resistance of SOI transistors. The experimental data for thermal conductivity of 50 nm copper layer is nearly a factor of three lower than the bulk values (400 W/m-K) at room temperature, which agrees well with a self-consistent model for heat and charge transport in thin copper layers. It is also concluded that the effective thermal resistance of multi-level copper-dielectric can largely impact the overall thermal resistance of small area (<100mum x 100 mum) transistor(s).