Quiescent current control circuit for class AB amplifiers

Among the several types of amplifiers in analog design, we find the Class AB amplifier. In this type of amplifier, the quiescent bias current in the output devices has a major impact in the power dissipation. Controlling the bias current represents a, major limitation, as it depends on other characteristics in the circuit. The motivation of this dissertation is to develop a new technique to control the quiescent current in the output transistors. This technique consists in making a replica of part of the circuit and having it operate under static conditions to obtain the desired quiescent current for the output transistors. This is achieved with few additional devices.;The implementation of this technique in several Class AB designs is discussed. Also the Class AB performance of the amplifiers and the accurate control of the current in the output stage is analyzed to validate the operation of the implementation of this technique. In addition, a comparison between the performance of these designs is analyzed when used in different practical systems. To test the performance we needed systems that represent a low-impedance or a high-capacitive load. For this purpose we used an R-2R Digital-to-Analog Converter, a charge redistribution Digital-to-Analog Converter and a headphone speaker.;Simulations and experimental results show that Class AB operation is achieved with accurate quiescent current control when this technique is implemented in three different designs. These designs include, a transconductance amplifier, a conventional opamp using a battery as a level shift in the output devices, and a conventional Class AB buffer without bias current control. The implementation of this technique shows that some designs enhance the slew rate in a factor 5 compared to the conventional two-stage amplifier. They also enhance dramatically the output impedance by a factor 16500 compared to the conventional amplifier.;Simulation and experimental results from prototypes fabricated in a CMOS 0.5pm technology are provided to validate the performance of the proposed technique.