Low-power operation of microprocessor systems in the presence of process variation

With the scaling of MOSFET dimensions and the performance enhancement features in the MOSFET, semiconductor manufacturing variation has also increased. Because of process variation and other reliability issues, circuits tend to move away from the nominal operating point, therefore degrading the parametric yield of the circuits. To assess the impact of process variations on the parametric yield of integrated circuits, an accurate process variation detection scheme is needed. This dissertation presents a new process variation detection and compensation technique. This technique uses the difference of the rise and fall slew as another metric along with delay in order to determine the magnitude and the relative mismatch between the drive strengths of the NMOS and PMOS devices. The importance of considering both of these metrics is illustrated, and a new slew-rate monitoring circuit is presented for use in measuring the difference of rise and fall slew on the critical path of the circuit. The measurement sensitivity of fabricated slew-rate monitor in a 65nm IBM CMOS technology is 0.11 V/microsecond with 1089 pF as the output load of the slew-rate monitor.;Six compensation schemes based on the delay or slew as the detection metric, with the ability to apply forward and reverse body-biasing, are analyzed in a 65 nm IBM CMOS technology. These schemes are capable of adjusting the critical path delay of the die to within any desired delay, as has been shown here within +/- 3% of the nominal delay, while reducing the total power dissipation by an average of ~8% across various process corners.;The compensation scheme is also extended to the within-die variation scenario. The chip is partitioned into multiple regions with localized sensors and a centralized supply voltage control with region-specific bias control is introduced to mitigate the impact of within-die (WID) process variation. The compensation algorithm determines the minimum required global supply voltage and the optimal body-biasing voltages for the individual regions. For a representative testbed circuit, this method achieves an average yield of 95% compared to that of 60% for the uncompensated circuit, while containing power budget to less than 15% above nominal power across all process corners and keeping the critical path delay in all modules short enough to meet the desired frequency.