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Development of 3D VLSI integration technology using copper-plated through silicon vias, copper post assembly, and fluid cooling

Posted on:2010-01-27Degree:Ph.DType:Dissertation
University:University of ArkansasCandidate:Liu, YangFull Text:PDF
GTID:1441390002975194Subject:Engineering
Abstract/Summary:PDF Full Text Request
The University of Arkansas Three Dimensional Very Large Scale Integrated Circuit (UA 3D VLSI) chip stack was designed to dissipate more than 20 W/cm 2 of heat per layer, while providing short vertical connection by through silicon vias (TSVs) and copper posts. TSVs were fabricated by thinning the process wafer down to 100 mum from the backside after filling copper in blind vias with tapered sidewalls. 100-mum-tall copper posts were plated in photoresist molds on the wafer backside, and copper dams for cooling fluid were fabricated in the same steps. Known-good-dies were then picked and stacked by using copper-tin intermetallic. By chip stacking, chips were electrically connected and micro-fluid channels for coolant circulation were formed.;The die layer fabrication, post building, post bonding and thinned chip stacking results are reported in this dissertation. Failures in chip stacking were analyzed. A two-layer test vehicle was tested. The heat dissipation capability was proven to be higher than 20 W/cm2 per layer which was the target of the research.;The process integration described above were required to integrate various processes steps that had been developed previously, but exhibited problems when applied to the fabrication of a thermal test vehicle.;Process integration is reported in this dissertation. The via etching and filling processes were refined to improve the overall yield across the 125 mm wafer. A pattern etch process was developed to etch the plated copper overburden, so that the vias could be connected individually to the thin copper traces deposited in the succeeding step. Void-free wafer bonding, a uniform thinning process, and backside insulation steps were developed for uniform chip thickness. Copper post building and planarization steps were developed for uniform post height. The flip chip bonder was improved for thin chip stacking. The trade-offs and relationships among the processes were carefully handled to maximize the yield.
Keywords/Search Tags:Chip, Copper, Post, Vias, Process, Integration
PDF Full Text Request
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