Process Integration Technology Of Carbon Nanotube Vias For Integrated Circuit Interconnects

With the integrated circuit(IC) feature size decreased, both copper electromigrationresistance reducing for interconnection line and signal delay increasing in proportion to itshigher resistance make the circuit reliability decreased. Carbon nanotubes(CNTs) areattractive material for next generation IC interconnects due to the reason that they have noelectromigration and can carry high current density(1010A/cm2). Current studies show that ICinterconnection application of CNTs has some blocks, including high resistance andcompatibility with CMOS process. The preparation methods of CNTs vias structure for ICinterconnects were studied to integrate CNTs into vias designed in this paper.Fistly, the depostion conditions of TiN, SiO2and Cu films by Magnetron Sputtering wereimproved with four point probe method, step profiler, and atomic force microscopy(AFM).The TiN film with low electricresistivity of 1.14×10-6·m, the compact SiO2film withdeposition rate of 330 nm/h, and Cu film were used in vias structure. 3μm diameter vias andtop electrodes with the space of 4μm were formed by the optimized process ofphotolithography and wet etching.Secondly, well-aligned and high-density(about 3×1011cm-2) CNTs in vias were grown byradio frequency plasma enhanced chemical vapor deposition (RF-PECVD) using Fe–Alcatalysts. In order to obtain aligned high-density CNTs at low temperature, Fe, Fe-Ni andFe-Al alloys as catalyst prepared by ion beam sputtering, and the bias voltage of substrate onCNTs growth were studied. CNTs were characterized by Scanning electron microscopy(SEM), transmission electron microscopy (TEM) and catalysts by AFM. The results showedthat Fe catalyst was more active than others at lower temperature. The catalyst for theoptimized growth rate, density and diameter uniformity was Fe-Al alloy. The density of CNTswas estimated to be about two times than that on other catalysts. The smaller andwell-distributed catalysts could help to improve the density of CNTs. A larger bias voltagewas good for the growth rate. but it was more easily to obtain well-aligned CNTs throughimproving the density not bias voltage.Lastly，the complete structures of CNTs interconnect vias with electrodes were finishedby process integration. Semiconductor parameter analyzer measured the resistance values ofdifferent CNTs vias completed by process integration. The results showed about 16μmdiameter vias resistance increased as size decreased, were 0.88 .