Epitaxial Growth And Electrical Properties Of Vertical GaN UMOSFET

At present,GaN-based power devices are widely used in the low-medium voltage range,which occupies a large part of the consumer electronic market.And for the high voltage range,the development of high-voltage GaN power devices mainly depends on the bulk GaN single crystal growth and vertical power devices.This thesis focuses on GaN vertical trench MOSFET(UMOSFETs),which is an attractive device structure due to the normally-off operation,the absence of a JFET region and the capability of high cell density.However,GaN UMOSFETs also have inherent undesired factors and there are challenges to be overcome in terms of epitaxy,process development,and structure optimization.This thesis will concentrate on the fabrication and characterization of GaN UMOSFETs,including epitaxial conditions improvement,the dependence of electrical characteristics and trench etching process,and the design of novel device structures.A preliminary study on the CAVET(current aperture vertical electron transistor)has also been done.The details are as follows:1.The interface pollution can be improved by annealing treatment before MOCVD regrowth on the GaN templates.After in-situ annealing at 1180? for 900 s,the C-V measurement shows that the background carrier concentration decreases by an order of magnitude compared with that without annealing treatment.2.The introduction of edge dislocation and the unintentional incorporation of carbon in GaN by tuning the MOCVD growth condition have been studied.The GaN films with the sheet resistivity of 106?/? are grown with nitrogen as nucleation layer carrier gas at low pressure and low ?/? ratio.GaN HEMTs based on the above-mentioned GaN as the buffer layers are also fabricated and show a ON/OFF ratio of 0.96×108,a breakdown voltage of 621 V.3.Process optimization of U-shape trench dry etching has been done.The etching gas flow rate,RF power and etching masks are varied and AFM is applied to investigate the etching rate,trench morphology and surface roughness.The micro-trench profile due to ion reflection effects is observed in the sample with the photoresist etching mask.Better trench morphology with a steeper sidewall and smaller surface roughness is observed in the SiO2 marked sample.Also,the effect of tetramethylammonium hydroxide(TMAH)treatment on the non-polar m-plane {1100} and ?-plane {1120}has been studied.Ga atoms on the m-plane are more easily removed by OH-and therefore much smoother m-plane sidewall can be obtained.4.Based on the above work,GaN UMOSFETs with a strip structure featuring interdigitated electrodes and in a hexagonal grid structure with m-plane and a-plane sidewall channels are fabricated and characterized.The device fabricated in a strip structure shows a saturation current of 226 A/cm2,a field-effect channel mobility of 72 cm7/V·s,a breakdown voltage of 400 V and an on-resistance of 4.0 m?·cm2.The model of on-resistance has been analyzed and built.The premature breakdown of gate dielectrics under reverse bias is due to the positive valence band offset between GaN and SiO2 and hence holes experience a barrier at the GaN/SiO2 interface.Consequently,the increased electric field in the dielectric layer leads to premature breakdown.Besides,improved electric characteristics of GaN UMOSFETs have been obtained with lower RF power and SiO2 etching mask.The interface state density is 2.65 X 1012 cm-2eV'1 when the RF power regulates to 50 W,only half of that when RF power is 135 W.GaN UMOSFETs with a hexagonal grid structure can increase the gate width per unit area and achieve high cell density,which can lay the foundation for fabrication of high power UMOSFETs.Field-effect channel mobility in m-plane-oriented MOS channel devices is 1.8 times that ofa-plane devices.Besides,m-plane devices also show a lower interface state density,a smaller subthreshold swing and a lower on-resistance.5.Three novel device structures have been proposed using Silvaco TCAD simulation to improve the figure of merit.The influence of key parameters on the device figure of merit has also been discussed.Firstly,the GaN UMOSFET combining a p-GaN shielding layer and an n-GaN spreading layer has been studied.In the OFF state,the p-GaN shielding layer effectively reduces the electric field in the gate dielectric.And in the ON state,the bulk JFET resistance caused by the shielding layer is significantly reduced by the insertion of the spreading layer.Secondly,the UMOSFET with a superjunction drift layer has been discussed.The doping concentration in the superjunction is optimized to achieve charge balance and the max figure of merit is 5.23 GW/cm2.Based on the field limiting ring in lateral power device junction termination techniques,the p-GaN buried island in the drift region is introduced.The length and the doping concentration of p-GaN have been adjusted to optimize the electric field distribution and a figure of merit of 2.92 GW/cm2 is obtained.6.As for CAVETs,two device structures featuring Al ion-implanted GaN and Mg-doped p-GaN as current blocking layers have been investigated.The CAVETs based on p-GaN current blocking layers show better pinch-off characteristics with a saturation current of 631.7 A/cm2 and an ON/OFF ratio of 1.9×107.Finally,two structures are evaluated and the corresponding improvement method has been proposed.