Study On Processing Technology And Mechanism Of Laser Thermal Cleavage Wafer Under Water Cooling

With the development of various semiconductor technologies,the semiconductor wafer technology has drawn considerable research attention.After lithography,ion implantation,and electroplating,an integrated circuit is manufactured on a wafer.Before processing the next step(assembly and testing),the semiconductor wafer should be separated into chips.Silicon,sapphire,and some other brittle materials,which exhibit high hardness and are easy to fracture,are used as substrates.The wafer-processing methods currently in use include mechanical wheel scribing,laser ablation scribing,water-jet-guided laser scribing,and stealth dicing.But the grinding wheel wear seriously because of the hardness under processing.High cost and wide kerf width reduce the utilization ratio of the wafer.The advantages of laser ablation scribing are low cost and high efficiency;however,this process produces a heataffected zone,which affects the surface quality of the material.Stealth dicing is a new laser processing method.After the stealth dicing process,the luminous efficiency of an light-emitting diode decreases;therefore,it is necessary to find a method that meets the demands of semiconductor wafer processing,which includes reducing the possibilities of producing a heat-affected zone in the material surface and thus improving the surface quality.In this study,laser processing under water cooling condition was analyzed experimentally and via simulation.The key technologies of laser processing under water cooling condition were studied under different parameters.First,it was difficult to further improve the efficiency of laser ablation under water cooling conditions.Therefore,in this study,controllable laser thermal cleavage under water cooling conditions was simulated,and the processing principle was analyzed.During this process,thermal stress occurs in the material;thus,the temperature gradient was calculated.From the simulation results,it was found that the areas at both ends of the laser spot were under tensile stress,and the area in the middle of the laser spot was under compressive stress.The wafer was separated into chips because of Mode I crack propagation.The tensile stress varied under different cooling conditions and laser spots;therefore,laser ablation requires further optimization.Second,from the results of the experiment and simulation,it was found that the tensile stress too small to thermal cleavage.In cases of no crack propagation on the surface,it was difficult to separate the wafer as the stress was small.Stress was produced at the tip of the guide groove,which facilitated wafer cleavage.With an increase in the depth of the guide groove,the stress concentration was more obvious.Wafer cleavage was easier with increased groove depth.The guide groove was experimentally analyzed under different parameters,and with higher laser power,slower speed,and repeated ablation,the guide groove was observed to be deeper.Simultaneously,molten material piled up on the sides of the groove.High surface quality can be obtained by surface coating.Finally,wafer morphology and microstructure were characterized after the controllable laser thermal cleavage process.There were four layers in the cross section of controllable laser thermal cleavage: guide groove layer,heat-affected layer,stress cleavage layer,and gallium nitride layer.The cross section was smooth did not have a heat-affected zone.The luminous efficiency of controllable laser thermal cleavage was 9% higher than that of stealth dicing.Cleavage shift often occurs during the controllable laser thermal cleavage process.The theory of cleavage shift was analyzed in this study.Furthermore,the effect of processing parameters was analyzed.The automation degree of visual alignment of the current wafer was low.The alignment parameters should be adjusted for different kinds of wafers.To overcome this issue,in this study,a wafer alignment algorithm based on Fourier transform and a water alignment based on neural network were proposed.Using the proposed algorithms,the precision required for industrial production and versatility was achieved,thus eliminating the process of aligning parameters for various wafers.