QR Decomposition For Baseband Signal Processing Of Future Wireless Communication Systems

The exponential growth of wireless data services,mass terminals and constantly emerging application scenerios has triggered the investigation of wireless communication to implement higher capacity,lower processing latencyand more flexible.The MUMIMO technique greatly improves the communication capacity,the spectra efficiency and reliability.MU-MIMO technique,however,significantly increases the computational complexity of baseband signal processing,especially,the high performance precoding algorithm and MIMO detection algorithm have been the bottleneck of the wireless communication system.This thesis research on the QR decomposition,which widely used in the high performance precoding algorithm and MIMO detection algorithm,and aim at designing the hardware architecture of QR decomposition,which dovetails nicely with the demand of baseband signal processing of future wireless communication system.The research of this thesis can build the basis for these high performance algorithms to be deployed in the wireless communication system.In summary,this thesis makes the following contributions:1.The iteration look-ahead MGS(ILMGS)algorithm based on MGS algorithm is proposed.”zero” latency user experience provides higher demand for QR decomposition of baseband signal processing.Based on the MGS algorithm,which has the best processing latency performance of the existing QR decomposition algorithms,this thesis provides a novel ILMGS algorithm to further reduce the processing latency performance.The proposed ILMGS algorithm involves lots of division and the square root operation,that leads to vast amounts of hardware overhead.In order to reduce the hardware overhead,this thesis proposes an enhanced ILMGS(E-ILMGS)algorithm to eliminate the division and the square root operation by the piecewise polynomial approximation and Newton Raphson iteration.2.A hardware architecture based on the E-ILMGS algorithm is designed.To obtobtain higher throughout and lower processing latency,a QR decomposition hardware architecture of triangular systolic array(TSA)is designed based on the proposed E-ILMGS algorithm.The inherent characteristics show that it needs abundant hardware overhead.Therefore,this thesis also designs an iteration architecture based the designed TSA architecture for the lower throughout demand.The iteration architecture can significantly decrease the hardware overhead and do not effect the processing latency performance by multiplexing the kernel hardware modules.A fixed-point simulation system is built for the E-ILMGS algorithm to choice the perfect fixed-point format.Then,these designed hardware architecture is implemented in 0.13?m CMOS technique.The implementation results show that the designed hardware architectures based on the proposed E-ILMGS algorithm achieve the superior processing latency performance than the existing works.3.The parallel tiled QR decomposition algorithm is proposed for the future baseband signal processing.The flexible deployment of antenna and massive MIMO technique need the QR decomposition hardware architecture of future baseband signal processing to be more flexible.This thesis proposes a novel flexible parallel tiled QR decomposition algorithm for future baseband signal processing based on the existing parallel tiled QR decomposition algorithm.The tile size of the proposed algorithm is 2 × 2,and each domain only contain one tile,that can significantly increase the parallelism and support flexible antenna configuration.To decrease the processing latency of parallel tiled QR decomposition algorithm,this thesis proposes a modified E-ILMGS(ME-ILMGS)algorithm based on the inherent characteristics of QR decomposition to decrease the processing latency of bottleneck operations(GEQRT operation and TTQRT operation)of parallel tiled QR decomposition algorithm.4.A hardware architecture based on the proposed parallel tiled QR decomposition algorithm is designed.This thesis designs a QR decomposition hardware architecture based on the proposed parallel tiled QR decomposition.The designed architecture can achieve higher throughout,lower processing latency and more flexible than most of the existing QR decomposition hardware architectures.A fixed-point simulation system is built for the proposed parallel tiled QR decomposition to select the best fixed-point format.Then,the designed architecture is implemented in 0.13?m CMOS technique.The implementation results show that the processing latency performance and the processing efficiency performance of the designed QR decomposition hardware architecture both are better than most of the existing QR decomposition hardware architectures.To the best of our knowledge,the hardware architecture presented in this paper achieves the superior QR decomposition rate and flexibility performance to the existing QRD hardware architectures.Hence,the designed architecture nicely dovetails the future demand of baseband signal processing.In summary,this thesis optimizes the QR decomposition from two point of view,hardware architecture and algorithm,oriented the demand of future baseband signal processing.The designed hardware architectures achieve lower processing latency,higher throughout and more flexible than most of the existing works.The research of this thesis can significantly promote the deployment of the high performance precoding algorithm and MIMO detection algorithm in future wireless communication systems.