Analysis Of Software Feature And System Reliability For Multi-Core On-Chip Systems

With the extensive application of multi-core on-chip systems in mobile terminals and their increasing system tasks,the performance efficiency and reliability of reconfigurable on-chip networks and their multi-core systems have become an important factor restricting their promotion in mobile computing and related applications.In order to ensure the safe and stable execution of the entire system,it is necessary to carry out relevant theoretical analysis and technical practice research in software execution efficiency,system reliability,and task scheduling management.This paper firstly analyzes the characteristics of the software running on multi-core sys-tems in order to reduce the characteristics of the instruction set,and establishes different types of software execution models to optimize the prefetching efficiency of the system.Then based on the reliability analysis of the Cache coherence protocol,the fault model of the HCS on-chip network structure is established,which serves as a basis for improving the reliability of the multi-core system.Finally,the uncertainty of the task runtime is ana-lyzed for the race condition,and the corresponding optimization task scheduling algorithm is proposed.The main work contents and innovations of this paper are as follows:(1)In order to solving the low efficiency of existing software in the multi-core on-chip system,the process algebra and the symbolic logic method is used to analyze the software behavior based on the reduced instruction set.Combined with the Markov State Machine Model,different types of software features are combined.A description is given,and at the same time,feature extraction is performed using a random sampling optimization algorithm,thereby reducing the amount of calculation and thus improving the Cache hit rate.(2)In order to solving the reliability issues caused by the state transition in the protocol of the Cache coherence protocol in the on-chip network system,the fault tree model is used as a basis to analyze the failure of the coherence protocol,and at the same time,the HCS on-chip network structure is established using the k-terminal model.The system reliability model,thus analyzing the existing reliability problems of the existing protocol and verifying the advantage of the HCS on-chip network structure.(3)There is a competition relationship among task scheduling in multi-core systems,which leads to the incorrect result of the system operation.The uncertainty of parallel run-ning of tasks is studied based on the race condition as the basis,and the task is optimized by using the maximum entropy theory to eliminate this problem.Uncertain competition relationship,and finally through the verification of this task scheduling algorithm in the system execution time,throughput and other aspects have great advantages.Finally,based on the techniques and methods proposed in this paper,we design a set of development environment that can be verified on hardware and software.Through this environment,we provide solutions for the hardware design of multi-core on-chip systems.