Mechanism Of Surge And Electrostatic Protection Device And Research Of On-Chip Integration Experimental

With the development of integrated circuit process,the quantity of the transistors integrated on silicon wafer is further moving towards the law of post-Moore.However,the damage of electronic components caused by surge electrostatic current is increasing year by year.In this paper,the failure and protection mechanism of on-chip anti-surge electrostatic protective devices are studied.Based on 0.5μm CDMOS(Complementary and Double-Diffusion Metal-Oxide-Semiconductor)and 0.25μm BCD(Bipolar-CMOS-DMOS)process,a variety of on-chip ESD protection devices with different structures are designed and on-chip integration experimental researches are carried out in RS485 chip with power supply of 5 V and 3.3 V,respectively.During the process of the researches,this paper studies the following key problems.First,according to the characteristics that the forward trigger voltage of a single Zener diode is not high enough and the difference of the positive and negative trigger voltage is relatively large.The electrostatic protection scheme of RS485 bus chip with positive and negative signal range is studied.Second,the trigger voltage of the SCR(Silicon Controlled Rectifier)devices base on the CDMOS and BCD process is high,and the hold voltage is low,to some extent.The high trigger voltage devices will not be able to protect the kernel circuit and the low hold voltage devices may trigger latch-up effect in the ESD response process.How to improve these two contradictions through the structure and response principle of the device is the subject discussed in this paper.Third,this paper studies the multi-finger DDSCR(Double Direction Silicon Controlled Rectifier)devices and discusses how to increase the number of opening fingers and improves the uniform of the current discharging.Fourth,how to integrate ESD devices with RS485 chip to achieve high electrostatic protection of the whole chip is another subject discussed in this paper.This paper focuses on the following 4 parts on how to solve the key problems mentioned above and realize high robustness ESD protection devices and on-chip integrated system.(1)This paper studies the principle of ESD protective devices and conducts equivalent circuit simulation and analysis.Via studying the parasitic pathway of the devices,the parasitic parameters of such structures as serial diode,SCR device,DDSCR device and GGNMOS(Gate-Grounded N-channel Metal Oxide Semiconductor)are equivalent to circuit models.Comparative simulation analysis is conducted on the PW(P Well)/NW(N Well)type DDSCR devices based on 0.25μm BCD technique.The transient response shows that the holding voltage of DDSCR devices(Vh)changes with the base region sizes of NPN transistor and PNP transistor.And the base region size of NPN makes a remarkable impact.When the transient current of the simulation was limited at 0.3A,as the base region size of the parasitic NPN increased by 3μm,the clamping voltage increased by 2.41V;as the base region size of the parasitic PNP increased by 5μm,the clamping voltage increased by 1.85 V.(2)A kind of DDSCR device is proposes and improves in this paper.Process simulation is conducted to optimize the device structure.SILVACO tools are used to establish the structural model of the device and explore the control mechanism of the device’s triggering voltage(Vt)and the impact of Guard Ring on positive/negative holding voltage(Vh).PW/NWD(Deep N Well)type DDSCR devices are simulated based on 0.5μm technique.Its I/V curve suggests the triggering voltage(Vt)is controlled by the doping concentration of carriers on the avalanche breakdown surface to conduct cross-well injection on the breakdown surface of a PW/NW type DDSCR device,thus changing the original breakdown surface PW/NWD into P+/NWD and improving the Vt of the device;0.25μm technique is used to further study the impact of whether the guard ring of HV-NW(High Voltage N Well)/P+(in PW)device is connected to the cathode on the holding voltage.When the guard ring is connected to the cathode,backward holding voltage is lower than forward holding voltage.(3)The physical design of on-chip integrated ESD devices and the verification on the devices is finished in this paper.An ESD device of Zener diode series structure is realized based on 0.5μm process.The device area is 709μm×465μm.Meanwhile,TLP(Transmission Line Pulse)testing is made.The I/V curve indicates that the positive and negative ESD capacities of the device are 16.25kV and 19.17kV respectively.This structure possesses parasitic triode path and Darlington Effect.The positive and negative triggering voltages are 13.73V and 13.05V,which are smaller than the design values of 15.1V.The positive and negative ESD capacities of the cross-well injected P+/NWD type device based on 0.5μm process reach 16.25kV and 19.17kV respectively.The device size is 105μm*287μm.HV-NW/P+(PW)DDSCR device based on 0.25μm BCD process is tested.The positive and negative triggering voltages are 20.97V and 17.12V respectively,reaching the design target.(4)This paper finishes the on-chip system integration research,layout design,tape out verification and test analysis for the chip and ESD devices.It infers the ESD response path of RS485 chip drive circuit,proposes the self-defense system structure of RS485 chip by combining the response windows of ESD devices,and verifies the on-chip integration system with ESD protection co-provided by ESD devices and RS485 drive circuit.The positive and negative HBM protective capacities of the deivice base on 0.5μm process are 26.15kV and 23.69kV respectively.The total area of the drive circuit and ESD is 726.65μm*464.31μm.The positive and negative HBM protective capacities of the deivice base on 0.25μm process are 20.86kV and 17.88kV respectively.The total area of the drive circuit and ESD is 734.595μm*452.655μm.