Research On Dynamic Binary Translation Optimization

With the rapid development of embedded processors, binary code compatibility has become the main obstacle to a new processor architecture whether can occupy the market. The development of binary translation technology is not only effective solution to the binary code compatibility, but also can effectively reduce the complexity of the processor design. This article focuses on the key aspects of dynamic binary translation technology, content and innovation:1. This paper propose a highly efficient dynamic approach for "compare and condition branch" instruction pair, which occupy a large proportion of the program. This method extracts the "compare and condition branch" instruction pair in the source block dynamically and completes the instruction mapping by the inherent conditional dependencies of the target machine. This method avoids the complex process for these special instruction pair in the traditional method and improves the speed of translation and execution.2. This paper proposes a dynamic prediction algorithm based on the indirect jump target addresses correlation for the indirect jump. This algorithm predict the first query compare and jump block of the indirect jump chain according to the previous indirect jump dynamically, reduce the execution instructions when hit on the indirect jump chain, reduce the switching overhead and improve the performance of binary translation system. Also proposing a hybrid algorithm which combines dynamic prediction algorithm and software prediction algorithm, this method make full use of the advantages of the two algorithms.3. This paper proposes one high speed address translation method which is based on the memory access region attribute. This method identified memory access instructions of different region in the translation state and used different algorithm for different memory region. Consistency page translation algorithm is adopted for stack region, the algorithm map the source machine contiguous virtual page of stack area to the target machine continuous virtual page which make access only need to add a specific offset for the stack area access, reduce complexity address translation in the execution state. Complier time translation algorithm is adopted for instruction and data region, this algorithm only access the address translation table in the translation state to eliminate the complex address translation in the execution state. Also proposing implement method in different architecture for this algorithm.4. This paper proposes an accelerated instruction design based on common attribution of condition code instruction setting rule. By using these instructions, data analysis process of the traditional condition code processing algorithms will be reduced. This method also reduces translation overhead and the redundant generated instruction and improves the efficiency of the implementation of the translator. Proposing an efficient method for accelerated instruction when it implement in the co-processor. This method mark the co-processor instruction complete state in the main processor reorder buffer when it is created, while the co-processor instruction is transmitted to the co-processor. This method speed up the co-processor instruction retirement in the main processor reorder buffer and the execution of the co-processor instruction, reduce the bubble in the pipeline of the main processor and improve the overall performance of the processor.