Research On Dynamic Binary Translation Technology For Microprocessor Design

Microprocessor is the core component of a morden computer. With the improvement of microelectronics technology and computer architecture, performance of microprocessors grows rapidly in the last three decades. Successful utilization of computers in various areas has brought greate economic and social benefits.Accumulation of software has made binary code compatibility a critical issue for the success of a processor. Binary code compatibility also limits what new architecture techniques may be used in microprocessor design. The emerging technology of dynamic binary translation may achieve binary code compatibility effectively through a translation software running on the underlying hardware processing core. It provides a novel idea for designing microprocessors and lowers the demands on microelectronics manufacture and design.The dissertation focuses on the research of dynamic binary translation technology for microprocessor design. Based on a moderate hardware supported binary translation processor model, the dissertation proposes the adaptive translation construction algorithm and the multi-level adaptive dynamic optimization framework. By adapting to the program execution behavior, the proposed methods effectively improve the processor's performance. Thread level parallelism exploitation within dynamic binary translation processors is also discussed in the dissertation.The work of this dissertation includes:1. The dissertation thoroughly investigates the present researches on microprocessor architecture and dynamic binary translation technology. Several important projects and products are analyzed. One conclusion is that complete compatibility and high performance is the object of binary translation processor design.2. As the base of the research, the dissertaton proposes a binary translation processor model named Transtar. Transtar consists of the underlying hardware processing engine named Transtar Core, and the translation software layer (TSL) running over it. Transtar Core is a simplified VL1W processor with moderate hardware support for binary translation. TSL maps the source architecture resources onto the Transtar Core and translates the IA-32 integer instructions to VLIW for execution.3. Translation unit construction deeply affects the performance of binary translation systems. It decides which part of the program will be translated. A novel Adaptive Translation UnitConstruction (ATUC) algorithm is proposed in the dissertation. With the support of a hardware continuous commit address detection buffer, ATUC monitors the execution of the translated code segments and adjusts the translation units adaptively. ATUC guarantees the success execution ratio of the translated code segments and improves code efficiency as far as possible with very low profile cost.4. Based on detailed analysis of dynamic optimizations, the dissertation proposes a Multilevel Adaptive Dynamic Optimization (MADO) framework. In MADO, optimizations are performed on several levels. The thresholds of the optimiztions are selected adaptively according to the benefit-cost analysis and the execution time prediction.5. To exploit the thread-level parallelism in binary translation processors, a parallel binary translation model named Transtar-Para is proposed. Transtar-Para assigns the execution of the translation software to two processing units. Thus, tasks such as code translation, profile analysis and translation cache management are seperated from the critical execution path of the source architecture instructions.6. Two prototype systems are developed to verify the correctness and performance of the work above. The user-level dynamic binary translation system, Transtar-UL, translates the user-level IA-32 integer instructions to the target VLIWs and simulates their execution. It verifies the correctness of the translation procedure and the performance advantages of the algorithm and framework proposed in the dissertation. The complete system translation system named TransBochs implements parallel dynamic translation with two OS threads. It boots the Linux operation system successfully. TransBochs verifies the design of the Transtar Core and the correctness of the Transtar-Para model.Conclusively, binary translation in processor design is a promising technology. It achieves binary code compatibility while reducing the hardware design complexity. It is helpful to avoid the instruction set authorization and hardware design patent issues. Moreover, further performance improvement could be expected with dynamic optimizaion. This method is a feasible one for us to make high performance microprocessors with our own intelligence property.