Research On Delay Evaluation And Performance Optimization For2D-mcsh NoC Based On QoS

Billions of transistors have been integrated on one single chip has with semiconductormanufacturing developed to nano-level. Process dimension of IC will be decreased to10nm within two years from2015, which drive the development of SoC (System on Chip)from multi-core to many-core, from centralized storage to distributed storage, from2D to3D, the complexity of communication between cores increased accordingly. Traditionalcommunication architecture based on bus on-chip has been the bottle neck for improvingon-chip communication performance. In order to overcome the shortness of Bus, NoC(Network-on-Chip) has been standard communication architecture overwhelmingly inon-chip communication. NoC should provide performance guarantee for different traffic,for the elastic data flows such as E-mail and FTP etc., bandwidth should be guaranteedwith best effort to make better use the resources in the NoC, and then, improve the averageperformance for the network. While for the rigid traffic that is sensitive to time such asmultimedia data flows, NoC should meet the demand for end-to-end delay.We build up network models and evaluate the delay with the premise of guaranteeQoS in the thesis, applied correlative technique to optima the performance for the NoC.There are four aspects as following.First, researches of performance evaluation for NoC in the past, with the assumptionthat memories distributed uniformly in the network and fixed delay for read and write, oversimplistically memory model without any controller and scheduler, ignorance of the accessof network node to off-chip memory, the conclusions getted under the assumption is toooptimistic to use. To get accurate evaluation for chip-off DRAM (Dynamic Ram AccurateModel) downloaded from OCP-IP (Open Core Protocol-International Partnership) workgrouper, we program the code with C++and SystemC to model the platform, drive Noximby SPLASH-2benchmark, and then, the reliable and effective results for NoC accessmemory performance has been found out.Second, In NoC-based many-core architectures, a lot of processor cores and memoriesare integrated, thus leading to a large number of on-chip memory accesses. Becauseprocessor cores and memories reside in different nodes, the difference locations of thenodes results in the different communication distances of on-chip memory accesses hencecause their different latency. In this situation, some memory accesses possibly have greatlatency, affecting the system performance severely. Therefore, the latency equalization ofmemory access in NoC is studied, and a novel arbitration technique for memory access packets is proposed, which is based on the round-trip latency prediction. Firstly, thecongestion information in the subsequent routing path of memory access packets is used topredict their waiting latency in the future and then the round-trip latency are calculated.Secondly, the predicted round-trip latency are used to decide the arbitration for the memoryaccess packets contending for the same link. The proposed technique is designed andimplemented in the routers of mesh-based NoC. Experimental results show that, underdifferent network sizes and packet injection rates, compared with the classic Round-Robinarbitration mechanism, the proposed technique can greatly reduce the maximum latency,the average latency and the latency standard deviation of on-chip memory accesses, and isproved to achieve better latency equalization of memory access.Third, in general, decreasing average delay could improve system performance forsome elastic traffic to a degree, whereas for some rigid traffic such as video transactions, ifthe maximum delay of flowing is over-sized, the quality of the video playing would berapidly deteriorated. Under the condition, NoC should guarantee the end-to-end transformin the network. In the thesis, we analysis the characteristics for the input flows, and find atight arriving curve based on Network Calculus, then calculus the backlog for the flow atdifferent time in the system busy period,at last, we got a piece-linear precise serve curvefor GPS node in NoC. Compared with approximate serve curve, the results got by ourmethod is more tight and optimal.Finally, we build up a flow-control routing model for NoC based on NetworkCalculus. A flow controller has been set in every router, and a feedback has been done byfeedback the output from down-stream node to up-stream node connected directly. Byconstraining the volume of input data, network congestion is decreased. An optimal size ofbuffer in the router has been induced by analyzing the maxim delay and backlog based onthe precise service curve.In conclusion, we build up network element facing to different traffic with thepremise of QoS, evaluate delay function, and optimize the network performance.