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Research On Real-time Stere Matching Algorithems Based On System On Programmable Chip

Posted on:2015-06-05Degree:DoctorType:Dissertation
Country:ChinaCandidate:X ZhangFull Text:PDF
GTID:1228330434458915Subject:Mechanical and electrical engineering
Abstract/Summary:PDF Full Text Request
The major task of a binocular stereo vision system is to reconstruct the3D representation of the scene from the2D images captured by two cameras that are fixed with their optical axes parallel and separated by a certain distance. Comparing with other stereo vision methods, binocular stereo vision method has the advantage of high resolution of3D reconstruction precision, widely used for various scenes, robustness and simplicity.At present, the binocular stereo vision system mainly used in planet rover, robot autonomous navigation and unmanned driving for intelligent vehicle. The main reason for binocular stereo vision system seldom used in civilian areas is its unsatisfactory performance in real-time and robustness, espically the bad real-time performance in high-resolution applications (such as1024×768pixels and above). The most time-consuming step in stereo vision is stereo matching. Consequently, this thesis presents a critical study to improve the accuracy and real-time performance of the stereo matching. It brings favorable application value in applying the stere vision system in real life.In this thesis, a novel local stereo matching algorithm based on sparse census transform is proposed. The tranditional census transform of a pixel is computed by comparing the pixel at centred location p with the other pixels within a square window around p. The intensity of the centred pixel is replaced by the census pixel produced by the census transform. The data occupation of census pixel is increased a few times than original intensity value. The common sparse census transform is proposed to decrese the data occpation by comparing the pixel at centred location p with the few pixels within transform window, but it brings too little correlation infomation included in census pixel and bad matching pixels will increse in stereo matching stage. The proposed algorithm computes census pixel by comparing two pixels’ intensity at different locations around the p under consideration of the pixel distribution within the window and its different correlate influence on centred pixel. The data occupation of the result of the new algorithm is same with the original pixel intensity, but the correlate infomation incorportated in the census pixel is more than twice as common sparse census transform. This is improved the robustness and real time performance of the algorithm.A FPGA hardware circuit is proposed to speed the proposed stereo matching algorithm through analyzing and modeling the parallelism of stereo matching processes. We design a pipelined architecture and parallelize all the function modules in the hardware circuit. The stereo matching process, including census transform, hamming distance calculation, sum of hamming distance computation, cost correlation, disparity segregator and L-R checking are designed and implemented using a signal FPGA chip. The algorithm core has excellent real time performance and can achieve70fps@1024x768processing speed under60MHz working frequence.A system on chip architecture is proposed by utilizing the technology of SoPC, which combine the stereo matching algorithm module with a32-bit microprocessor and several peripherals in a single FPGA chip. The core of the system is32-bit Nios II microprocessor. It connects with DDRII SDRAM, SSRAM, Flash memory, PLL, JTAG UART, timer, pipelined reading DMA and stereo matching hardware circuit module by highspeed Avalon bus to constitute a special computer for stereo matching. The system provides a set of interface for user to config the working parameters of the stereo matching module. It enables the system can deals vairous stereo pictures with different resolutions.We implement sparse census transform based stereo matching algorithm and SAD stereo matching algorithm with the proposed SoPC architecture. The resourse consumption, process speed and matching accuracy of two algorithms are analyzed in method of comarison. The result demonstrates that the proposed stereo matching algorithm is better than SAD stereo matching algorithm in all aspects.
Keywords/Search Tags:Binocular stereo vision, stereo matching, programmable system on chip, FPGA, census transform, pipeline and parellel architecture
PDF Full Text Request
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