Research On Key Technologies Of Low Power SoC Design

As the advance of integrated circuits (ICs) and the wide applications of portable devices, power has becomeone of the primary design objective following area and performance. With the transistor or logic cell basedtraditional IC design techniques entering the IP-core based SoC design era, the subsequent hierarchical designmethod brings new challenges for power optimization. For the key technologies of low power SoC design, thedissertation studies multi-voltage SoC floorplanning in physical design stage, state assignment of finite statemachine (FSM) in logic design step, and the novel CMOS hybrid circuit in circuit level. The performance of theproposed optimization algorithms is validated by the benchmark suites. The main contents of the dissertationcontain the following sections:1. For the floorplanning in multi-voltage SoC design, an effective algorithm is proposed for poweroptimization and CPU time speedup. By relaxing the rectangular shaped constraint of voltage islands (VIs), thepower is reduced by the generation of nonrectangular shaped VIs. The CPU time is speedup by nonrandomizedsearching engine. In addition, the blocks with the same operating voltage are grouped by a hypergraph to furtherspeedup the VI generation. Experimental results show that the proposed algorithm has advantages on power,wirelength, deadspace, and CPU time.2. By considering the voltage drop problem in multi-voltage SoC power/ground (P/G) network, a fastpower pad assignment method is proposed based on spring model. Moreover, by exploring the key parameters inthe voltage drop closed form expression, a voltage drop aware power pad assignment and floorplanningco-synthesis method is proposed. Instead of matrix inversion to obtain the node voltage, a weighted distance fromblocks to power pads is used to evaluate the cost function. Finally, the topology of the P/G network is optimizedincrementally. Experimental results show the performance of P/G network is improved and the blocks and powerpads are placed in optimized locations.3. To solve the level shifters (LSs) placement in multi-voltage SoC design, a timing driven design flow isproposed. The voltage assignment, LSs placement, and VI generation are considered simultaneously under boththe timing and physical constraints. To reserve deadspace for LSs placement, the virtual LSs are inserted in thenetlist. Different from previous works which do not consider the physical impact on voltage assignment, thevoltage assignment and LSs placement are iteratively solved in the inner loop to make both timing and physicalconstraints be satisfied.4. For the sequential circuits in the IP core, a peak current and switching activity optimization algorithm isproposed based on Lagrangian relaxation technique. Genetic algorithm is adopted to search the solution space andsubgradient optimization method is used to update Lagrangian multipliers in each iteration. The peak currentupper bound is determined by a heuristic algorithm. By testing on IWLS’93and ITC’99benchmark suites, theproposed algorithm can optimize the peak current upto45.27%and25.13%compared to previous works,respectively. In addition, the switching activity is also reduced6.31%. Compared to deterministic method, it alsocan achieve the same peak current in even less CPU time.5. Regarding the novel CMOS hybrid circuit, mapping algorithm, the key step to implement SoC isstudied. By Lagrangian relaxation of the mapping problem, the solution space is searched by evolutionary algorithm which includes two-dimensional crossover, mutation and self-learning operators. Experimental resultsshow that the proposed method can solve larger circuit size, and obtain less area, timing and CPU time. Moreover,by considering the high fanout gate hard to be mapped, the logic restructuring method is proposed based on logicreplication and buffer insertion. Since the mapping complexity reduced, experimental results show theperformance is improved after restructuring.