High Speed Digital Pulse Uwb Wireless Transceiver System Research And Implementation

Along with the PAD computer, smartphone, digital set-top boxes, digital camera, DVD, digital vidicon, HDTV and other consumer electronic products widely spreading, short-distance high-speed wireless communications between electronic products, has been a hot topic. IR-UWB system employs an extreme narrow pulse to transmit data. The advantages of non-carrier modulation communication mode, which has always been a focus among academia and research institutions, are low power and low complexity. Currently, academic researches on IR-UWB are concentrated on applications mainly about the biological health, ranging found,and location,where the transimission rate is less than10MHz, even a few KHz. UWB has the advantage of transimmision rate up to500Mb/s,which other short-range wireless transmission technology are uncompared with. The UWB research about high-speed data transmission rate in industry principally focuses on OFDM and DS-CDMA schemes, which having been widely used in narrowband communication as their proven technique; but lacking innovation. This paper focuses on IR-UWB system appling on short-range high-speed data transmission. As traditional IR-UWB architecture could not handle the inter-symbol interference at high speed, it is unsuitable for high-speed data transmission. Learning from the design ideas of the SDR, this article presents a low accuracy, subsampling and digital IR-UWB system for high-speed wireless transmissions.The receiver and transmitter of the proposed digital IR-UWB system don’t need mixeres. In the receiver, the input UWB RF signal is amplified through the LNA and VGA, then ADC directly samples the RF signal at the low precision of less than4bit and the rate lowering than Nyquist rate. All the signal processing is completed by the digital baseband. The structure has the advantages of low power and low complexity. On the basis of the architecture study, this paper systematically studied digital baseband algorithm based on the training code, and gives the achieving algorithms including the channel estimation, synchronization, channel equalization and etc. This paper proposes a joint algorithm based on training code polarity sequence synchronization and threshold channel estimation. At the same time, a complete system solution, including the realization of the digital baseband algorithms and RF circuit, is given. The feasibility of digital IR-UWB system is demonstrated by the system modeling and simulation.Finally, a lbit low precision and sampling rate at4224MHz IR-UWB transceiver is presented. The highest physical transimission rate is132Mb/s, and the effective data transmission rate is114Mb/s. The transceiver RF circuits are implemented in SMIC0.13μm CMOS process with the supply of1.2V. The energy-efficient transmitter and receiver only consume18.2pJ/pulse and330pJ/pulse to achieve a transmission at a date rate of132Mb/s, respectively. The BPSK modulation transmitter employs a RLC circuit to shape the pulse spectrum, and pulse parameters can be adjusted continuously by adjusting the resistance R. The measurement results show that the pulse spectrum of3～5GHz is consistent with the FCC spectrum. The pulse width is between900ps and1600ps, and its amplitude is between110mV and370mV. LAN, VGA, ADC, PLL and clock divider are all integrated. The ADC is composed of16time interleaving comparators, which operating at the low frequency of 264MHz. The test results show that the ADC is lbit operating at the frequency of4224MHz,and the LNA and VGA gain coefficient is16dB～28dB. And the noise figure is less than3.7dB. The16output channels of ADC receiving signal from the LNA input is match with the simulation well and can provide16bits parallel input signals samping at the frequency of264MHz to the digital baseband. The digital circuit has integrated the entire system of digital baseband algorithms and embeds an MCU soft IP core for auxiliary control and code processing.The functional verification of digital baseband is completed in FPGA development board.The results show that the baseband circuit can automatically reset in the unsynchronized case; and demodulate data correctly.The best bit error rate is5x10-4.The digital baseband system is integrated in SMIC0.13m CMOS process. The operating frequency is264MHz and the total power is902.3mW.